79 lines
1.6 KiB
Markdown
79 lines
1.6 KiB
Markdown
# 📡 RFSoC Channelizer + PS Processing (R-ESM Prototype)
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## Overview
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This project is based on the RFSoC SoC Blockset reference design, adapted as a prototype for a Radar Electronic Support Measures (R-ESM) receiver.
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The system implements a high-throughput signal chain in the FPGA (PL) and performs frame-based processing in the processor (PS).
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---
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## Current Status
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- Tx subsystem: LFM pulse generator (DDS-based, complex output)
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- Rx subsystem: fully functional channelizer pipeline (PFB-based)
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- PL → PS interface: AXI4-Stream + DMA operational
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- PS processing: frame-based algorithm (RMS + peak detection)
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## System Architecture
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ADC → Channelizer (PFB, 512 bins)
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→ FFT_Capture (frame control)
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→ FIFO Serializer (4 FIFOs → 1 stream)
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→ AXI4-Stream (uint64)
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→ DMA (S2MM)
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→ PS Memory
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→ Processor Algorithm
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## Key Parameters
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- ADC Sampling Rate: 4096 MSPS
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- Decimation: 8
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- Effective BW: 512 MHz
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- Channels (FFT size): 512
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- Samples per clock: 4
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- FPGA clock: 128 MHz
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- Frame size (PS): 512 samples
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---
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## 📚 Documentation
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### FPGA (PL)
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- [Tx Subsystem (Pulse Generator)](docs/pl_tx_subsystem.md)
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- [Rx Subsystem (Channelizer)](docs/pl_rx_subsystem.md)
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### Processor (PS)
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- [PS Subsystem](docs/ps_subsystem.md)
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---
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## System Flow
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Tx → Rx → PS
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- Tx generates waveform
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- Rx captures and channelizes
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- PS processes frames
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## Roadmap
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1. Functional FrFT (PS)
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2. Profiling
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3. NEON optimization
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4. Throughput tuning
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5. PL acceleration
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---
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## Key Takeaway
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First make it work end-to-end, then make it fast. |