309 lines
5.2 KiB
Markdown
309 lines
5.2 KiB
Markdown
# RFSoC Channelizer RX Architecture (ZCU111)
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> **Project Context:** This design is part of a prototype **R-ESM (Radar Electronic Support Measures) receiver**, implemented on the ZCU111 RFSoC platform.
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> The project was initiated from the RFSoC reference template provided by MATLAB/Simulink SoC Blockset and is being incrementally analyzed and modified.
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---
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## System Overview
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* The **TX subsystem** is currently used for test purposes:
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* Generates a **single-tone signal via NCO**
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* Future work: implement an **LFM pulse generator**
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* The **RX subsystem** (focus of this document):
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* Acquires RF data via ADC
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* Performs **channelization (PFB)**
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* Buffers and serializes data
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* Streams data to processor (PS) via AXI DMA
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---
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## System Configuration
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* ADC Sampling Rate: **4096 MSPS**
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* Decimation: **×8 → 512 MSPS effective bandwidth**
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* FPGA Fabric Clock: **128 MHz**
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* Samples per Clock: **4 complex samples**
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---
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## Channelizer (PFB)
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* Type: Polyphase Filter Bank (PFB)
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* Number of Channels: **512**
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* Taps per Channel: **16**
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* Output per Clock:
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* `4 complex samples` (vectorized)
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* `valid`, `SOF`, `EOF`
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### Frame Structure
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* Total bins per frame: **512**
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* Samples per clock: **4**
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* → **128 clock cycles per frame**
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### Time-Multiplexed Output
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Each clock produces consecutive frequency bins:
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```id="y7l3sj"
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clk 0 → bins 0–3
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clk 1 → bins 4–7
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...
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clk 127 → bins 508–511
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```
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---
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## Data Representation
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* Input to channelizer: **16-bit complex**
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* Output: **25-bit complex**
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* Per sample: **50 bits (Re + Im)**
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Data is later packed into **uint64** for AXI compatibility.
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---
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## FIFO Architecture (Banked Design)
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### Structure
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* **4 independent FIFOs**
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* One FIFO per lane (sample index)
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```id="k6d9c7"
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Lane 0 → FIFO1
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Lane 1 → FIFO2
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Lane 2 → FIFO3
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Lane 3 → FIFO4
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```
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### Depth
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* Each FIFO depth: **128**
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* Total frame: **512 samples**
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* → 512 / 4 = 128 samples per FIFO
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---
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## Why 4 FIFOs (Critical Design Choice)
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### Hardware Constraint
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FPGA BRAM:
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* Max **2 ports**
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* Cannot support **4 simultaneous writes**
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### Input Requirement
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* 4 samples per clock → **4 writes per clock**
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### Solution
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→ **Banked memory (4 FIFOs)**
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Each FIFO:
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* 1 write per clock
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* Fully compatible with BRAM architecture
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---
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## Data Organization Across FIFOs
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Each FIFO stores a decimated sequence of bins:
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```id="ehy2k6"
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FIFO1: bins 0, 4, 8, ...
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FIFO2: bins 1, 5, 9, ...
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FIFO3: bins 2, 6, 10, ...
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FIFO4: bins 3, 7, 11, ...
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```
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This is a **lane-based de-interleaving** of the channelizer output.
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---
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## Serialization (Parallel → Stream Conversion)
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### Input
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* 4 samples per clock (parallel)
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### Output
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* 1 sample per clock (AXI stream)
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### Mechanism
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A **FIFO Sequencer** performs round-robin reads:
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```id="b42g8p"
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Cycle 0 → FIFO1
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Cycle 1 → FIFO2
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Cycle 2 → FIFO3
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Cycle 3 → FIFO4
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(repeat)
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```
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### Result
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Reconstructed stream:
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```id="9f8x7x"
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0, 1, 2, 3, 4, 5, ..., 511
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```
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---
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## Throughput Behavior
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* Write side: **4 samples/clk**
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* Read side: **1 sample/clk**
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Over 4 cycles:
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* 4 samples written → 4 samples read
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→ **No data loss (rate preserved over time)**
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---
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## TLAST Handling (Frame Boundary)
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* TLAST is embedded in FIFO data:
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* LSB of FIFO word carries TLAST flag
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```id="l6g0vn"
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[Data (50 bits)] + [TLAST (1 bit)]
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```
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* Extracted after FIFO mux and sent to AXI
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### Behavior
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* TLAST asserted **once per frame**
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* Typically associated with final bin (e.g., bin 511)
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---
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## AXI4-Stream Interface
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Output signals:
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* `tdata` → uint64 packed data
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* `tvalid` → data valid
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* `tready` → backpressure from DMA
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* `tlast` → frame boundary
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### Data Path
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```id="9m7iqk"
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PL → AXI4-Stream → AXI DMA (S2MM) → DDR → PS
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```
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---
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## Backpressure Handling
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AXI backpressure (`tready`) propagates upstream:
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* If `tready = 0`:
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* FIFO reads pause
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* Data accumulates in FIFOs
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### Protection Mechanism
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* FIFO_Sequencer only reads when:
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* AXI is ready
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* Data available in all FIFOs
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---
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## Triggered Capture Mechanism
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### Trigger Source
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* Software writes to register
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* Generates 1-cycle pulse (`TriggerCapture`)
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### FFT_Capture Behavior
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State machine:
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```id="27qf3x"
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IDLE → wait trigger
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ARMED → wait SOF
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CAPTURE → collect 128 cycles
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DONE → assert TLAST
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```
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### Key Property
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Capture is **frame-aligned** (starts at SOF)
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---
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## Architectural Pattern
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The system implements:
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```id="2q6v6x"
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Parallel Stream (4 samples/clk)
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↓
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Banked Memory (4 FIFOs)
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↓
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Round-Robin Serialization
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↓
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AXI Stream (1 sample/clk)
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```
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This is a standard FPGA pattern:
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> **Lane-based parallelism + memory banking + time-multiplexed output**
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---
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## Notes for Future Work (FrFT Integration)
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### Recommended Insertion Points
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**Option A (Preferred):**
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```id="bb7jbp"
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FIFO output → FrFT → MUX → AXI
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```
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**Option B:**
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```id="o5o0qz"
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MUX → FrFT → AXI
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```
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### Avoid
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```id="q8k3yo"
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Before FIFOs (requires 4-sample parallel processing)
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```
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---
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## Key Takeaways
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* Multiple FIFOs are required due to **memory port limitations**
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* Serialization is done via **deterministic round-robin scheduling**
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* AXI backpressure is safely absorbed using FIFO buffering
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* Frame integrity is guaranteed via **SOF-aligned capture + TLAST**
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* Architecture is scalable and suitable for further DSP insertion (e.g., FrFT)
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---
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