Zcu111ResmReceiver/docs/pl_tx_subsystem.md

📡 PL Tx Subsystem (Pulse & Continuous LFM Generator)

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Overview

The Tx subsystem implements a pulse-based and continuous Linear Frequency Modulated (LFM) chirp generator using a DDS/NCO architecture in the FPGA (PL).

The generator produces complex baseband output:

x[n] = exp(j·φ[n])

and operates deterministically in the PL after a trigger from the PS.

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Architecture

TxPulseStart (PS) ↓ pulse_gen_ctrl (FSM) ↓ tx_active ↓ Phase Increment Logic ↓ NCO (DDS) ↓ Complex Output (I/Q)

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Operating Modes

The subsystem now supports multiple Tx modes:

1. Pulsed LFM (default)

• Chirp generated only during pulse window
• Phase resets at each pulse start
• Standard radar burst operation

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2. CW Mode (Continuous Wave)

• tx_active = 1 continuously
• Generates a single-tone output
• Achieved by setting constant phase increment

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3. Continuous LFM (Workaround Implementation)

• tx_active forced HIGH continuously
• A 1-cycle LOW pulse is inserted periodically
• This LOW→HIGH transition resets the NCO

Result:

• Continuous chirp
• Bounded bandwidth
• Periodic repetition of LFM

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Chirp Generation Principle

The chirp is generated using a second-order phase accumulator:

Δφ[n] = Δφ[n−1] + step
φ[n] = φ[n−1] + Δφ[n]

This results in a linear frequency sweep.

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Parameterization (PS → PL)

Inputs:

• Center frequency: Fc
• Bandwidth: B
• Pulse width: N (samples)

Derived internally:

f_start = Fc − B/2
step = B / (N − 1)

These values are converted to DDS phase increments before being written to PL registers.

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Pulse Timing (FSM)

States:

• IDLE: waits for trigger and latches parameters
• ACTIVE: generates pulses
• DONE: waits for trigger reset

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Timing Behavior

Pulsed Mode

|<------ PRI ------>| |<-- pulse -->| idle |

• tx_active = 1 → chirp output
• tx_active = 0 → output zero

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Continuous LFM Mode

tx_active behavior:

1 1 1 1 1 0 1 1 1 1 ...

• 1-cycle LOW inserted at end of chirp period
• Rising edge resets NCO
• Defines chirp repetition interval

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CW / Continuous LFM Implementation Details

• CW mode bypasses FSM output
• A dedicated counter generates periodic reset pulses
• Reset timing is based on pulse_width_cycles

Important:

• Reset pulse is exactly 1 clock cycle
• Ensures deterministic NCO restart
• Decoupled from PRI/FSM timing

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Burst Trigger (PS Interaction)

• Controlled via TxPulseStart (memory-mapped register)
• Rising edge triggers burst
• PL runs autonomously afterward

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Key Characteristics

• Deterministic timing (128 MHz)
• Efficient DDS (adder-based)
• Complex output (I/Q)
• Supports:
  • Pulsed radar mode
  • Continuous wave (CW)
  • Continuous LFM (periodic chirp)

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Design Notes

• FSM controls timing (when to transmit)
• NCO controls frequency evolution
• Continuous LFM implemented via tx_active edge reuse
• Minimal hardware overhead (no additional NCO logic)

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🔗 Related Components

• 🏠 Project Home
• PL Rx Subsystem
• PS Subsystem