295 lines
5.5 KiB
Markdown
295 lines
5.5 KiB
Markdown
# 🧠 PS Subsystem (Control + Capture + Processing)
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[🏠 Project Home](../README.md)
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---
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## Overview
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The PS subsystem is responsible for:
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* System initialization
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* Configuring PL subsystems
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* Triggering captures
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* Receiving data via DMA
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* Preparing data for processing and visualization
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The subsystem now includes an initial **FrFT-based processing chain** implemented in Simulink and targeted to the RFSoC Processing System (PS).
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Current work focuses on:
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* Algorithm validation
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* Code generation
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* Hardware integration
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* Performance characterization
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while maintaining reliable data acquisition and host interaction.
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---
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## Responsibilities
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### Control & Initialization
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* Configure PL parameters:
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* Tx waveform configuration
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* Capture parameters (nFrames, etc.)
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* Initialize DMA and memory buffers
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* Manage system startup
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### Trigger & Capture
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* Generates capture trigger (software-controlled)
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* Controls DPW acquisition timing
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* Each trigger initiates one DPW capture
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---
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### DMA Handling
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* AXI4-Stream → DMA (S2MM)
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* Receives **128-bit stream** (4 samples per clock)
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* Stores data in PS DDR memory
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Configuration:
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* Frame size: 512 samples
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* nFrames: configurable (validated up to 1024)
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---
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## Data Format
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### Raw DMA Data
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* Packed complex samples
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* 16-bit real + 16-bit imag per sample
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* 4 samples per 128-bit word
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---
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### Processing Representation
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Data is unpacked and reshaped into:
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```text
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[FrameSize x nFrames x nTriggers]
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```
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or, for processing purposes,
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```text
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[FrameSize x nFrames]
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```
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representing a single DPW.
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---
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## Processing Pipeline (Current)
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```text
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DMA
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↓
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Unpack samples (I/Q separation)
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↓
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Convert to complex representation
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↓
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Reshape into DPW matrix
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↓
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Processing Path Selection
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Path A:
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Polyphase Filter Bank (PFB)
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↓
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Power Spectrum
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Path B:
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FFT
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↓
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Power Spectrum
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Path C:
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FrFT
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↓
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Mean Power Spectrum
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↓
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Visualization / Analysis
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```
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---
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## FrFT Processing Status
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A first FrFT processing implementation has been integrated into the PS subsystem.
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### Processing Flow
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```text
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DPW [512 x nFrames]
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↓
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Halfband Interpolation (2x)
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↓
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FrFT Coefficient Generation
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↓
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DPW-Aware FrFT Processing
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↓
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Mean Power Spectrum
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```
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### Software Structure
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```text
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codegen_fracFdpw/
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│
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├── fracF_init.m
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├── fracF_dpw.m
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├── TBc_fracFdpw.m
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└── TBm_fracFdpw.slx
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```
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### Validation Completed
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* DPW-aware FrFT implementation created
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* Verified against original `fracF_cg`
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* Bit-identical equivalence achieved
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* MATLAB testbench (TBc) created
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* Simulink model testbench (TBm) created
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* TBc ↔ TBm comparison automated
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* Bit-identical TBc ↔ TBm validation achieved
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* Standalone subsystem code generation validated
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* RFSoC PS integration completed
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### Current Status
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The implementation is functionally correct and integrated into the RFSoC processing chain.
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Current work is focused on:
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* Performance characterization
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* FrFT parameter optimization
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* Realistic pulse processing scenarios
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### Open Technical Questions
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The matched-order formulation used in the SPL simulations assumed:
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```text
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Observation Window = Pulse Duration
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```
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The receiver currently operates under a different condition:
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```text
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Observation Window < Pulse Duration
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```
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where only a portion of the pulse is processed by the FrFT.
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Additional investigation is required to determine:
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* Optimal FrFT order for partial-pulse observations
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* Practical DPW sizes
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* Trade-off between concentration and processing load
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* Deviation from idealized SPL simulation conditions
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### Current Limitations
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* Coefficients are regenerated every execution
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* No coefficient caching implemented
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* No NEON-specific optimization
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* Generated FFT kernels are used
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* Performance scales strongly with DPW size
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---
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## Validation Support
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Uses counter-based validation:
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* Real part → sample counter
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* Imag part → frame index
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Enables verification of:
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* Data continuity
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* Frame alignment
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* Correct ordering from DMA
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---
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## Execution Model
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* Triggered (event-based)
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* Burst capture (DPW)
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* Not continuous real-time streaming
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---
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## Performance Notes
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Current implementation prioritizes correctness and validation over optimization.
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Observations from RFSoC integration:
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* FrFT processing successfully executes on the RFSoC PS
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* nFrames = 64 executes responsively
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* nFrames = 1024 remains computationally expensive
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* Processing load scales approximately linearly with DPW size
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* Code generation and subsystem integration have been validated
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Current optimization candidates:
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* Coefficient caching when FrFT order remains unchanged
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* NEON vectorization
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* Alternative FFT implementations
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* DPW size optimization
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---
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## Role in System
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The PS currently serves as:
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* Control interface
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* Data acquisition manager
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* Signal processing platform
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* Algorithm development and validation environment
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Current processing capabilities include:
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* PFB-based spectral analysis
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* FFT-based spectral analysis
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* FrFT-based spectral analysis
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---
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## Future Work
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### FrFT
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* Matched-order optimization for realistic pulse captures
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* Performance profiling on RFSoC PS
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* Coefficient caching
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* NEON optimization
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* Detection processing after FrFT concentration
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### System
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* Timestamp integration
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* UDP streaming
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* Metadata extraction
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* Migration of computationally intensive functions to PL where appropriate
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---
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## 🔗 Related Components
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* [🏠 Project Home](../README.md)
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* [PL Tx Subsystem](pl_tx_subsystem.md)
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* [PL Rx Subsystem](pl_rx_subsystem.md)
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