135 lines
2.0 KiB
Markdown
135 lines
2.0 KiB
Markdown
# 📡 PL Rx Subsystem (Channelizer)
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[🏠 Project Home](../README.md)
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---
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## Overview
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The Rx subsystem implements a **polyphase filter bank (PFB) channelizer** followed by FFT processing.
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It converts wideband ADC input into frequency-domain channels and streams the result to the PS.
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A **bypass path** is also available for raw data inspection and debugging.
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---
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## Architecture
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### Channelizer Path (default)
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ADC
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↓
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PFB Channelizer (Decimation + Filtering)
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↓
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FFT (512 bins)
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↓
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FFT Capture
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↓
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FIFO Serializer (4 → 1)
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↓
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AXI4-Stream
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↓
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DMA
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---
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### Bypass Path (Debug / Raw Data)
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ADC
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↓
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Bypass Path
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↓
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FIFO / Serializer
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↓
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AXI4-Stream
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↓
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DMA
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---
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## Bypass Functionality
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The bypass allows direct observation of the input signal without channelization.
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### Purpose
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- Debugging and validation
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- Access to raw ADC-domain data
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- Comparison with channelized output
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- Verification of downstream processing
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---
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### Behavior
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- Input data is routed directly to output
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- No filtering or FFT applied
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- Maintains same output interface (AXI4-Stream)
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---
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### Selection Mechanism
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A selector signal chooses between:
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- Channelizer output (normal operation)
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- Bypass output (raw data)
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Implementation typically uses:
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- Parallel paths
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- Output switching logic
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---
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## Processing Chain (Channelizer Mode)
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### ADC Input
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- Sampling rate: 4096 MSPS
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### PFB Channelizer
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- Decimation: 8
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- Effective bandwidth: 512 MHz
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### FFT
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- Size: 512
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- Produces frequency bins
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### FFT Capture
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- Controls frame boundaries
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### FIFO Serializer
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- Converts parallel streams into single stream
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---
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## AXI4-Stream Output
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- Data type: uint64
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- Packed real/imag
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- TLAST = frame boundary
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---
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## Data Format
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- Frame size: 512 samples
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- Complex values packed into uint64
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---
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## Key Characteristics
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- Fully streaming pipeline
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- High throughput
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- Deterministic latency
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- Supports dual-mode operation (channelizer / bypass)
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---
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## 🔗 Related Components
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- [🏠 Project Home](../README.md)
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- [PL Tx Subsystem](pl_tx_subsystem.md)
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- [PS Subsystem](ps_subsystem.md)
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