📡 RFSoC Channelizer + PS Processing (R-ESM Prototype)
Overview
This project is based on the RFSoC SoC Blockset reference design, adapted as a prototype for a Radar Electronic Support Measures (R-ESM) receiver.
Current Status
- Tx subsystem: simple tone generator (to be replaced by LFM pulse generator)
- Rx subsystem: fully functional channelizer pipeline (PFB-based)
- PL → PS interface: AXI4-Stream + DMA working
- PS processing: frame-based algorithm (RMS + peak detection)
System Architecture
ADC → Channelizer (PFB, 512 bins) → FFT_Capture (frame control) → FIFO Serializer (4 FIFOs → 1 stream) → AXI4-Stream (uint64) → DMA (S2MM) → PS Memory → Processor Algorithm (frame-based)
Key Parameters
- ADC Sampling Rate: 4096 MSPS
- Decimation: 8
- Effective BW: 512 MHz
- Channels (FFT size): 512
- Samples per clock: 4
- FPGA clock: 128 MHz
- Frame size (PS): 512 samples
DMA (PL → PS)
- Data type: uint64
- Frame size: 512
- Buffers: 16
- Memory: PS DDR
Each TLAST corresponds to one DMA frame.
Processor (PS)
- Event-driven execution (triggered by DMA)
- No task queueing
- Frames may be dropped if processing is slower than input rate
Data Path in PS
- Stream Read → uint64[512]
- Bit extraction → real/imag
- Conversion → complex vector
- Processing → RMS + peak detection
Performance Notes
- Bottleneck: unpacking + type conversion
- PS cannot keep up with full-rate stream
- Frames are skipped under load
FrFT Integration Plan
- Replace Processor Algorithm with FrFT
- Keep all other components unchanged
- Input: complex single [512x1]
- Accept dropped frames initially
Roadmap
- Functional FrFT (PS)
- Profiling
- NEON optimization
- Throughput tuning
- PL acceleration
Key Takeaway
First make it work end-to-end, then make it fast.