canisio 43f91b281b Tested on board. Running ok. Updated interface model and added shortcut to it.

2026-03-27 17:52:13 -03:00

..

Abllu374wtDd3IliE-5ZoGpf8mM

- Added utilities for frequency planning

2026-03-27 12:50:10 -03:00

EEtUlUb-dLAdf0KpMVivaUlztwA

Initial

2026-03-24 12:44:45 -03:00

fjRQtWiSIy7hIlj-Kmk87M7s21k

Initial

2026-03-24 12:44:45 -03:00

KAXfQgCar2Yb8zOxgvf9hdmLP1E

Tested on board. Running ok. Updated interface model and added shortcut to it.

2026-03-27 17:52:13 -03:00

NjSPEMsIuLUyIpr2u1Js5bVPsOs

Initial

2026-03-24 12:44:45 -03:00

OMhPU_mfqqvzwvxt1vnyR5RoJhM

Initial

2026-03-24 12:44:45 -03:00

qaw0eS1zuuY1ar9TdPn1GMfrjbQ

Changed NCO on AD/DA to 0Hz. Changed language for HDL IP to Verilog. Cleaned up for new soc_prj generation

2026-03-25 18:23:42 -03:00

root

Initial

2026-03-24 12:44:45 -03:00

Project.xml

Initial

2026-03-24 12:44:45 -03:00

rootp.xml

Initial

2026-03-24 12:44:45 -03:00

uuid-51cebdc6-9979-4c34-b2d4-3c553bcad0dd.xml

Initial

2026-03-24 12:44:45 -03:00