canisio d5bbdfb435 Changed NCO on AD/DA to 0Hz. Changed language for HDL IP to Verilog. Cleaned up for new soc_prj generation

2026-03-25 18:23:42 -03:00

..

Abllu374wtDd3IliE-5ZoGpf8mMd.xml

Initial

2026-03-24 12:44:45 -03:00

Abllu374wtDd3IliE-5ZoGpf8mMp.xml

Initial

2026-03-24 12:44:45 -03:00

C1ER3pVluvJGF_Xdyk9mqiPj37Yd.xml

Added sw interface model (controls hardware running on board).

2026-03-25 17:21:09 -03:00

C1ER3pVluvJGF_Xdyk9mqiPj37Yp.xml

Added sw interface model (controls hardware running on board).

2026-03-25 17:21:09 -03:00

OMhPU_mfqqvzwvxt1vnyR5RoJhMd.xml

Initial

2026-03-24 12:44:45 -03:00

OMhPU_mfqqvzwvxt1vnyR5RoJhMp.xml

Initial

2026-03-24 12:44:45 -03:00

VuQUU2B038bh2-Z0EHHaJtE6ir0d.xml

Changed NCO on AD/DA to 0Hz. Changed language for HDL IP to Verilog. Cleaned up for new soc_prj generation

2026-03-25 18:23:42 -03:00

VuQUU2B038bh2-Z0EHHaJtE6ir0p.xml

Changed NCO on AD/DA to 0Hz. Changed language for HDL IP to Verilog. Cleaned up for new soc_prj generation

2026-03-25 18:23:42 -03:00

zl4c0tdESbRAbW_oAp1iPTJvRUQd.xml

Changed NCO on AD/DA to 0Hz. Changed language for HDL IP to Verilog. Cleaned up for new soc_prj generation

2026-03-25 18:23:42 -03:00

zl4c0tdESbRAbW_oAp1iPTJvRUQp.xml

Changed NCO on AD/DA to 0Hz. Changed language for HDL IP to Verilog. Cleaned up for new soc_prj generation

2026-03-25 18:23:42 -03:00