canisio c10736a5d7 AXI4-S2Software>Main>Advanced>Interconnect: Data width (bits) changed to 128

2026-04-24 12:14:14 -03:00

..

soc_rfsoc_fpga.slx

AXI4-S2Software>Main>Advanced>Interconnect: Data width (bits) changed to 128

2026-04-24 12:14:14 -03:00

soc_rfsoc_proc.slx

FPGA Packer: Changed to uint128, changed endianess order of packing (selectors 4,3,2,1)

2026-04-24 11:59:16 -03:00