canisio beb5410390 added visualisation to validate ouput of multiple frames

2026-04-16 11:56:25 -03:00

..

9q0RC5MfaA5JiLrN2zU0hbRN-KYd.xml

Added startup function to project (setup HDL tool on it)

2026-03-25 16:15:16 -03:00

9q0RC5MfaA5JiLrN2zU0hbRN-KYp.xml

Initial

2026-03-24 12:44:45 -03:00

Fd9H20iNQ049h3heONYKHGeEV4Ud.xml

Oganize preload and init functions and parameters (ongoing)

2026-04-04 15:16:58 -03:00

Fd9H20iNQ049h3heONYKHGeEV4Up.xml

Added startup function to project (setup HDL tool on it)

2026-03-25 16:15:16 -03:00

JApHYjRonL4iH_Lt47VmbReaSokd.xml

Changed NCO on AD/DA to 0Hz. Changed language for HDL IP to Verilog. Cleaned up for new soc_prj generation

2026-03-25 18:23:42 -03:00

JApHYjRonL4iH_Lt47VmbReaSokp.xml

Changed NCO on AD/DA to 0Hz. Changed language for HDL IP to Verilog. Cleaned up for new soc_prj generation

2026-03-25 18:23:42 -03:00

tCT0PPSsb_pWf9AZXBgbx9rTu4Ad.xml

Initial

2026-03-24 12:44:45 -03:00

tCT0PPSsb_pWf9AZXBgbx9rTu4Ap.xml

Initial

2026-03-24 12:44:45 -03:00

tPKcWOiWJbBj2scfmbdefBYs6Qwd.xml

Initial

2026-03-24 12:44:45 -03:00

tPKcWOiWJbBj2scfmbdefBYs6Qwp.xml

Initial

2026-03-24 12:44:45 -03:00