canisio ea0ecefae1 Added documentation and updated README

2026-04-02 17:29:24 -03:00

..

9lwM0dX3iyjMhadwFjZ2rmFpFrEd.xml

Added frft functions towards codegen (c code on PS)

2026-03-30 11:16:12 -03:00

9lwM0dX3iyjMhadwFjZ2rmFpFrEp.xml

Added frft functions towards codegen (c code on PS)

2026-03-30 11:16:12 -03:00

Abllu374wtDd3IliE-5ZoGpf8mMd.xml

Initial

2026-03-24 12:44:45 -03:00

Abllu374wtDd3IliE-5ZoGpf8mMp.xml

Initial

2026-03-24 12:44:45 -03:00

C1ER3pVluvJGF_Xdyk9mqiPj37Yd.xml

Added sw interface model (controls hardware running on board).

2026-03-25 17:21:09 -03:00

C1ER3pVluvJGF_Xdyk9mqiPj37Yp.xml

Added sw interface model (controls hardware running on board).

2026-03-25 17:21:09 -03:00

F2x-oreEzd1RuWtdF_H3bxSqbsMd.xml

added placeholder for chirp block

2026-04-01 12:05:57 -03:00

F2x-oreEzd1RuWtdF_H3bxSqbsMp.xml

added placeholder for chirp block

2026-04-01 12:05:57 -03:00

MEnu9bsvaE1ht88eLRvHOJK-Wu0d.xml

Pulse Generator TB validated

2026-04-02 17:08:44 -03:00

MEnu9bsvaE1ht88eLRvHOJK-Wu0p.xml

Pulse Generator TB validated

2026-04-02 17:08:44 -03:00

OMhPU_mfqqvzwvxt1vnyR5RoJhMd.xml

Initial

2026-03-24 12:44:45 -03:00

OMhPU_mfqqvzwvxt1vnyR5RoJhMp.xml

Initial

2026-03-24 12:44:45 -03:00

QMJD9OLFzxcTTbPOoh-ahQ4zTRUd.xml

added README

2026-03-27 18:41:29 -03:00

QMJD9OLFzxcTTbPOoh-ahQ4zTRUp.xml

added README

2026-03-27 18:41:29 -03:00

rW25SbP5jRWeIzL7_iMpZrrygYkd.xml

Added documentation and updated README

2026-04-02 17:29:24 -03:00

rW25SbP5jRWeIzL7_iMpZrrygYkp.xml

Added documentation and updated README

2026-04-02 17:29:24 -03:00

VuQUU2B038bh2-Z0EHHaJtE6ir0d.xml

Changed NCO on AD/DA to 0Hz. Changed language for HDL IP to Verilog. Cleaned up for new soc_prj generation

2026-03-25 18:23:42 -03:00

VuQUU2B038bh2-Z0EHHaJtE6ir0p.xml

Changed NCO on AD/DA to 0Hz. Changed language for HDL IP to Verilog. Cleaned up for new soc_prj generation

2026-03-25 18:23:42 -03:00

zl4c0tdESbRAbW_oAp1iPTJvRUQd.xml

Changed NCO on AD/DA to 0Hz. Changed language for HDL IP to Verilog. Cleaned up for new soc_prj generation

2026-03-25 18:23:42 -03:00

zl4c0tdESbRAbW_oAp1iPTJvRUQp.xml

Changed NCO on AD/DA to 0Hz. Changed language for HDL IP to Verilog. Cleaned up for new soc_prj generation

2026-03-25 18:23:42 -03:00