Changed NCO on AD/DA to 0Hz. Changed language for HDL IP to Verilog. Cleaned up for new soc_prj generation

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canisio

2026-03-25 18:23:42 -03:00

parent 89c8003f5a

commit d5bbdfb435

12 changed files with 14 additions and 6 deletions

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referencedmodels/soc_rfsoc_fpga.slx

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referencedmodels/soc_rfsoc_proc.slx

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