This website requires JavaScript.
Explore
Help
Register
Sign In
canisio
/
Zcu111ResmReceiver
Watch
1
Star
0
Fork
0
You've already forked Zcu111ResmReceiver
Code
Issues
Pull Requests
Actions
Packages
Projects
Releases
Wiki
Activity
5
Commits
1
Branch
0
Tags
d5bbdfb435960874d4e48a8a64faf3eea34004c0
Go to file
Code
Clone
HTTPS
Tea CLI
Open with VS Code
Open with VSCodium
Open with Intellij IDEA
Download ZIP
Download TAR.GZ
Download BUNDLE
canisio
d5bbdfb435
Changed NCO on AD/DA to 0Hz. Changed language for HDL IP to Verilog. Cleaned up for new soc_prj generation
2026-03-25 18:23:42 -03:00
referencedmodels
Changed NCO on AD/DA to 0Hz. Changed language for HDL IP to Verilog. Cleaned up for new soc_prj generation
2026-03-25 18:23:42 -03:00
resources
/project
Changed NCO on AD/DA to 0Hz. Changed language for HDL IP to Verilog. Cleaned up for new soc_prj generation
2026-03-25 18:23:42 -03:00
utilities
Added startup function to project (setup HDL tool on it)
2026-03-25 16:15:16 -03:00
.gitattributes
Initial
2026-03-24 12:44:45 -03:00
.gitignore
Initial
2026-03-24 12:44:45 -03:00
BeamForming.prj
Initial
2026-03-24 12:44:45 -03:00
gm_soc_rfsoc_top_sw.slx
Changed NCO on AD/DA to 0Hz. Changed language for HDL IP to Verilog. Cleaned up for new soc_prj generation
2026-03-25 18:23:42 -03:00
soc_rfsoc_top.slx
Changed NCO on AD/DA to 0Hz. Changed language for HDL IP to Verilog. Cleaned up for new soc_prj generation
2026-03-25 18:23:42 -03:00
Description
Test model for a R-ESM I/Q receiver with 512MHz of instantaneous bandwidth on ZCU111 RFSoC
2
MiB
Languages
MATLAB
100%
