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Changed NCO on AD/DA to 0Hz. Changed language for HDL IP to Verilog. Cleaned up for new soc_prj generation

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canisio
2026-03-25 18:23:42 -03:00
parent 89c8003f5a
commit d5bbdfb435
12 changed files with 14 additions and 6 deletions
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resources/project/qaw0eS1zuuY1ar9TdPn1GMfrjbQ/VuQUU2B038bh2-Z0EHHaJtE6ir0d.xml
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<?xml version='1.0' encoding='UTF-8'?>
<?xml version="1.0" encoding="UTF-8"?>
<Info>
<Category UUID="FileClassCategory">
<Label UUID="design"/>

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resources/project/qaw0eS1zuuY1ar9TdPn1GMfrjbQ/VuQUU2B038bh2-Z0EHHaJtE6ir0p.xml
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<?xml version='1.0' encoding='UTF-8'?>
<?xml version="1.0" encoding="UTF-8"?>
<Info location="soc_rfsoc_top.slx" type="File"/>

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resources/project/qaw0eS1zuuY1ar9TdPn1GMfrjbQ/zl4c0tdESbRAbW_oAp1iPTJvRUQd.xml Normal file
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<?xml version='1.0' encoding='UTF-8'?>
<Info>
<Category UUID="FileClassCategory">
<Label UUID="design"/>
</Category>
</Info>

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resources/project/qaw0eS1zuuY1ar9TdPn1GMfrjbQ/zl4c0tdESbRAbW_oAp1iPTJvRUQp.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<Info location=".slx" type="File"/>