7 Commits

Author	SHA1	Message	Date
canisio	10644b0475	added README	2026-03-27 18:41:29 -03:00
canisio	89ecf79e61	Added comment os PS system. Info from training says the time-driven tasks are all inside the processor block, except the event driven and the initialize	2026-03-27 17:17:28 -03:00
canisio	13263f4f33	Removed one of the channels and respective beamforming on Tx and Rx. Simulation ok. Kept the read registers of the angles as placeholders for future use.	2026-03-27 16:51:41 -03:00
canisio	584db6233c	- Added utilities for frequency planning ... - Changed freq plane to: Fs 4096, int/dec 8X, Mixers 768	2026-03-27 12:50:10 -03:00
canisio	d5bbdfb435	Changed NCO on AD/DA to 0Hz. Changed language for HDL IP to Verilog. Cleaned up for new soc_prj generation	2026-03-25 18:23:42 -03:00
canisio	c86497656b	Changed fs to 1024MSPS and added double-sided spectrum visualization. FFT Shifit with two selectors and one concatenate	2026-03-24 18:10:26 -03:00
canisio	ac2e7bcece	Initial	2026-03-24 12:44:45 -03:00