canisio
edef1dbed3
validation: add checkCounterSamples and verify capture up to 1024 frames on ZCU111
...
Created checkCounterSamples.m to validate sample continuity, counter wraps,
and frame index progression. Verified counter bypass, sine bypass, and
channelizer modes up to nFrames=1024 across 10 DPWs on ZCU111.
2026-04-27 18:32:31 -03:00
canisio
cb56e78923
changed folder name for all testbench models
2026-04-17 08:31:14 -03:00
canisio
2e570cee8b
Created folder and test bench model for new capture block. Copied from current version.
2026-04-08 15:50:59 -03:00
canisio
ea0ecefae1
Added documentation and updated README
2026-04-02 17:29:24 -03:00
canisio
e810145620
Pulse Generator TB validated
2026-04-02 17:08:44 -03:00
canisio
790c2fdb37
added placeholder for chirp block
2026-04-01 12:05:57 -03:00
canisio
e0765a6afe
Added bypass funcion and its testbench (bypass folder)
2026-03-31 14:25:43 -03:00
canisio
7b04d52204
Added frft functions towards codegen (c code on PS)
2026-03-30 11:16:12 -03:00
canisio
10644b0475
added README
2026-03-27 18:41:29 -03:00
canisio
d5bbdfb435
Changed NCO on AD/DA to 0Hz. Changed language for HDL IP to Verilog. Cleaned up for new soc_prj generation
2026-03-25 18:23:42 -03:00
canisio
89c8003f5a
Added sw interface model (controls hardware running on board).
2026-03-25 17:21:09 -03:00
canisio
ac2e7bcece
Initial
2026-03-24 12:44:45 -03:00
