canisio
2b8f8de030
Validation of multiframe on TBm_capture done.
2026-04-15 17:52:09 -03:00
canisio
9fd110f451
Replace serializer with 128-bit packer and add MultiFrameCapture (testbench)
...
Removed FIFO serializer and implemented 128-bit AXI packing (4 samples/beat)
Added initial MultiFrameCapture FSM
Validated with counter input
Sine/channelizer validation pending (frame interpretation update needed)
2026-04-14 17:56:57 -03:00
canisio
aad231b55a
AXI with 128 bits and no serializer appears to be working
2026-04-14 16:46:18 -03:00
canisio
3748b65872
implemented sample packer to construct 128 AXI. Partially working (only bypass works?)
2026-04-14 12:25:01 -03:00
canisio
d83006c50c
Added counter as input for the TBm_capture
2026-04-14 10:32:02 -03:00
canisio
5e5bba3ce6
Stable 16-bit Q1.15 Rx chain before AXI width upgrade
2026-04-14 09:25:01 -03:00
canisio
ccc6b9cd73
Validate 16-bit Q1.15 Rx chain (baseline, partial validation)
...
Standardized ADC/DAC and channelizer input to fixdt(1,16,15)
Rescaled channelizer output from sFix25_En23 to 16-bit complex
Verified channelizer path and spectrum behavior in full simulation
Bypass path and datatype tuning (coefficients/output) pending validation
2026-04-13 17:47:08 -03:00
canisio
f221e14c2c
updated Rx documentation
2026-04-13 16:47:42 -03:00
canisio
a01186484e
Rx: standardize to Q1.15 and reduce channelizer output to 32-bit complex
...
- ADC/DAC set to fixdt(1,16,15)
- Channelizer output scaled from sFix25_En23 to Q1.15
- Data width reduced from 50b to 32b
- Validated channelizer and bypass paths
Model: TBm_capture.slx
2026-04-13 16:47:25 -03:00
canisio
4241699c3d
TBm_caputre. changed PFB internals and output datatype
2026-04-09 12:43:32 -03:00
canisio
d4e53a67ee
Stable single frame (512 samples) baseline before capture redesign
2026-04-09 09:27:44 -03:00
canisio
2e570cee8b
Created folder and test bench model for new capture block. Copied from current version.
2026-04-08 15:50:59 -03:00
canisio
f8edb31dc2
updated doc: Tx subsystem
2026-04-08 15:04:15 -03:00
canisio
520a37f520
CW mode integrated to design
2026-04-08 15:00:47 -03:00
canisio
cd91e3066b
added CW mode (with LFM) to the chirp block (TB, not integrated yet)
2026-04-08 12:19:03 -03:00
canisio
5a3bc8891d
cleaned up log signals (still not working)
2026-04-07 09:26:50 -03:00
canisio
fdde9ec62b
Initiliaze funcion back to 1 (in the toggle registers). Still not working
2026-04-06 17:39:05 -03:00
canisio
84b795203a
pulse generator integrated but not working
2026-04-06 16:16:42 -03:00
canisio
ada7e324cd
Fixed register address on "update parameters"
2026-04-06 15:15:55 -03:00
canisio
7813d9744c
Modified PS part and interface towards pulse generation integration
2026-04-06 12:26:06 -03:00
canisio
05b74503dc
Fixed init callback for pulse gen testbench
2026-04-06 10:45:21 -03:00
canisio
72b9a34db9
Ready to move from sine to pulse generator (Tx Subsystem)
2026-04-06 10:23:23 -03:00
canisio
3c6ae0cfe9
finished organization of init funcions and parameters
2026-04-04 16:05:17 -03:00
canisio
eb14676581
Oganize preload and init functions and parameters (ongoing)
2026-04-04 15:16:58 -03:00
canisio
040834d511
added docs folder to project path.
...
tested remotely. OK
2026-04-03 20:47:13 -03:00
canisio
a92709b500
Added bypass of channelizer to the documentation
2026-04-02 17:39:01 -03:00
canisio
27ec12161c
detailed subsystems
2026-04-02 17:36:23 -03:00
canisio
5caaa7fd9a
updated README
2026-04-02 17:32:03 -03:00
canisio
ea0ecefae1
Added documentation and updated README
2026-04-02 17:29:24 -03:00
canisio
e810145620
Pulse Generator TB validated
2026-04-02 17:08:44 -03:00
canisio
a82aed0d5a
Changed NCO to complex on TBm_chirp
2026-04-02 16:43:03 -03:00
canisio
62ab58b741
Changed Update parameter subsystem on chirp TB to pulse fc and pulse BW.
2026-04-02 16:28:41 -03:00
canisio
8e397fa41e
Added draft to TBm_chirp model. Added init function script to testbench
2026-04-02 12:03:59 -03:00
canisio
790c2fdb37
added placeholder for chirp block
2026-04-01 12:05:57 -03:00
canisio
872fbfcd6e
Minor changes
2026-04-01 11:51:59 -03:00
canisio
9794b2d540
tested on HW. Bypass ok.
2026-03-31 18:47:13 -03:00
canisio
b72a8cd616
added time scope to interface
2026-03-31 18:00:27 -03:00
canisio
f66c3ffd06
Changed interface model to reflect bypass
2026-03-31 17:51:26 -03:00
canisio
0c6938bff2
commented initialize register on proc model
2026-03-31 17:25:01 -03:00
canisio
66ad6149e6
Added switch and led (physical)
2026-03-31 16:41:27 -03:00
canisio
a9b4ad9e17
Added bypass toggle via memory mapped register
2026-03-31 16:17:34 -03:00
canisio
0ea6881d1e
Added bypass to Rx on FPGA. Test OK
2026-03-31 15:55:46 -03:00
canisio
278e318715
Added simulink model to testbench bypass funcion (bypass folder)
2026-03-31 14:26:45 -03:00
canisio
e0765a6afe
Added bypass funcion and its testbench (bypass folder)
2026-03-31 14:25:43 -03:00
canisio
dd70d58f2a
Added frtt_codegen folder to the project initialization
2026-03-31 09:19:28 -03:00
canisio
d8a9e026ff
Added testbench for simulink model. Added f0 option to both testbenches
2026-03-30 16:01:46 -03:00
canisio
1613ae8ad9
Ran codegen for mex and tested. Working ok
2026-03-30 11:44:31 -03:00
canisio
7b04d52204
Added frft functions towards codegen (c code on PS)
2026-03-30 11:16:12 -03:00
canisio
30b31509c1
Updated README
2026-03-30 09:30:16 -03:00
canisio
10644b0475
added README
2026-03-27 18:41:29 -03:00
