6 Commits

Author	SHA1	Message	Date
canisio	43f91b281b	Tested on board. Running ok. Updated interface model and added shortcut to it.	2026-03-27 17:52:13 -03:00
canisio	584db6233c	- Added utilities for frequency planning ... - Changed freq plane to: Fs 4096, int/dec 8X, Mixers 768	2026-03-27 12:50:10 -03:00
canisio	d5bbdfb435	Changed NCO on AD/DA to 0Hz. Changed language for HDL IP to Verilog. Cleaned up for new soc_prj generation	2026-03-25 18:23:42 -03:00
canisio	89c8003f5a	Added sw interface model (controls hardware running on board).	2026-03-25 17:21:09 -03:00
canisio	7c1292ae5c	Added startup function to project (setup HDL tool on it)	2026-03-25 16:15:16 -03:00
canisio	ac2e7bcece	Initial	2026-03-24 12:44:45 -03:00