canisio
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5a3bc8891d
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cleaned up log signals (still not working)
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2026-04-07 09:26:50 -03:00 |
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canisio
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fdde9ec62b
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Initiliaze funcion back to 1 (in the toggle registers). Still not working
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2026-04-06 17:39:05 -03:00 |
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canisio
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84b795203a
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pulse generator integrated but not working
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2026-04-06 16:16:42 -03:00 |
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canisio
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ada7e324cd
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Fixed register address on "update parameters"
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2026-04-06 15:15:55 -03:00 |
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canisio
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7813d9744c
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Modified PS part and interface towards pulse generation integration
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2026-04-06 12:26:06 -03:00 |
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canisio
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3c6ae0cfe9
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finished organization of init funcions and parameters
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2026-04-04 16:05:17 -03:00 |
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canisio
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eb14676581
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Oganize preload and init functions and parameters (ongoing)
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2026-04-04 15:16:58 -03:00 |
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canisio
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9794b2d540
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tested on HW. Bypass ok.
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2026-03-31 18:47:13 -03:00 |
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canisio
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f66c3ffd06
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Changed interface model to reflect bypass
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2026-03-31 17:51:26 -03:00 |
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canisio
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66ad6149e6
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Added switch and led (physical)
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2026-03-31 16:41:27 -03:00 |
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canisio
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a9b4ad9e17
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Added bypass toggle via memory mapped register
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2026-03-31 16:17:34 -03:00 |
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canisio
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0ea6881d1e
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Added bypass to Rx on FPGA. Test OK
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2026-03-31 15:55:46 -03:00 |
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canisio
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d8a9e026ff
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Added testbench for simulink model. Added f0 option to both testbenches
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2026-03-30 16:01:46 -03:00 |
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canisio
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10644b0475
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added README
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2026-03-27 18:41:29 -03:00 |
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canisio
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89ecf79e61
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Added comment os PS system. Info from training says the time-driven tasks are all inside the processor block, except the event driven and the initialize
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2026-03-27 17:17:28 -03:00 |
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canisio
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13263f4f33
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Removed one of the channels and respective beamforming on Tx and Rx. Simulation ok. Kept the read registers of the angles as placeholders for future use.
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2026-03-27 16:51:41 -03:00 |
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canisio
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7c361a9608
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Prepare to remove one of the channels. The idea is to transform the beamforming project in a simple wideband detector.
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2026-03-27 13:24:50 -03:00 |
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canisio
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584db6233c
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- Added utilities for frequency planning
- Changed freq plane to: Fs 4096, int/dec 8X, Mixers 768
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2026-03-27 12:50:10 -03:00 |
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canisio
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d5bbdfb435
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Changed NCO on AD/DA to 0Hz. Changed language for HDL IP to Verilog. Cleaned up for new soc_prj generation
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2026-03-25 18:23:42 -03:00 |
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canisio
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89c8003f5a
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Added sw interface model (controls hardware running on board).
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2026-03-25 17:21:09 -03:00 |
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canisio
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c86497656b
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Changed fs to 1024MSPS and added double-sided spectrum visualization. FFT Shifit with two selectors and one concatenate
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2026-03-24 18:10:26 -03:00 |
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canisio
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ac2e7bcece
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Initial
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2026-03-24 12:44:45 -03:00 |
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