canisio
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2e570cee8b
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Created folder and test bench model for new capture block. Copied from current version.
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2026-04-08 15:50:59 -03:00 |
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canisio
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3c6ae0cfe9
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finished organization of init funcions and parameters
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2026-04-04 16:05:17 -03:00 |
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canisio
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eb14676581
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Oganize preload and init functions and parameters (ongoing)
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2026-04-04 15:16:58 -03:00 |
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canisio
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040834d511
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added docs folder to project path.
tested remotely. OK
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2026-04-03 20:47:13 -03:00 |
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canisio
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ea0ecefae1
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Added documentation and updated README
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2026-04-02 17:29:24 -03:00 |
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canisio
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e810145620
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Pulse Generator TB validated
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2026-04-02 17:08:44 -03:00 |
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canisio
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8e397fa41e
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Added draft to TBm_chirp model. Added init function script to testbench
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2026-04-02 12:03:59 -03:00 |
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canisio
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790c2fdb37
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added placeholder for chirp block
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2026-04-01 12:05:57 -03:00 |
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canisio
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f66c3ffd06
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Changed interface model to reflect bypass
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2026-03-31 17:51:26 -03:00 |
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canisio
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278e318715
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Added simulink model to testbench bypass funcion (bypass folder)
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2026-03-31 14:26:45 -03:00 |
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canisio
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e0765a6afe
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Added bypass funcion and its testbench (bypass folder)
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2026-03-31 14:25:43 -03:00 |
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canisio
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dd70d58f2a
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Added frtt_codegen folder to the project initialization
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2026-03-31 09:19:28 -03:00 |
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canisio
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d8a9e026ff
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Added testbench for simulink model. Added f0 option to both testbenches
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2026-03-30 16:01:46 -03:00 |
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canisio
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1613ae8ad9
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Ran codegen for mex and tested. Working ok
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2026-03-30 11:44:31 -03:00 |
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canisio
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7b04d52204
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Added frft functions towards codegen (c code on PS)
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2026-03-30 11:16:12 -03:00 |
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canisio
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10644b0475
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added README
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2026-03-27 18:41:29 -03:00 |
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canisio
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43f91b281b
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Tested on board. Running ok. Updated interface model and added shortcut to it.
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2026-03-27 17:52:13 -03:00 |
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canisio
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584db6233c
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- Added utilities for frequency planning
- Changed freq plane to: Fs 4096, int/dec 8X, Mixers 768
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2026-03-27 12:50:10 -03:00 |
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canisio
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d5bbdfb435
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Changed NCO on AD/DA to 0Hz. Changed language for HDL IP to Verilog. Cleaned up for new soc_prj generation
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2026-03-25 18:23:42 -03:00 |
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canisio
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89c8003f5a
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Added sw interface model (controls hardware running on board).
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2026-03-25 17:21:09 -03:00 |
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canisio
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7c1292ae5c
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Added startup function to project (setup HDL tool on it)
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2026-03-25 16:15:16 -03:00 |
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canisio
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ac2e7bcece
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Initial
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2026-03-24 12:44:45 -03:00 |
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