canisio
91b02cdc79
organized register... stopped working
2026-04-20 11:53:26 -03:00
canisio
0b1dc081e5
commented display on PS, before testing in the board
2026-04-20 10:51:08 -03:00
canisio
b2ce956f41
Multi-frame capture integrated into full design with trigger-controlled DPW; AXI stream (uint32 [4x1]) and DMA framing aligned; fixed FSM termination condition (no overflow); validated end-to-end (PL→DMA→PS) using counter input for multiple nFrames
2026-04-17 17:03:34 -03:00
canisio
fc50e71ab5
AXI stream updated to uint32 [4x1] format; samples-per-frame aligned to nFrames×512; PS stream read configured accordingly; single-frame (nFrames=1) validated end-to-end (PL→DMA→PS) with correct unpacking and data integrity
2026-04-17 12:22:12 -03:00
canisio
ce87190fba
If sw side of AXI4-Stream to Software block is set to fixdt(128), frames appear to be arriving correctly on PS. However, reinterpretation is failing when using option "uint32"
2026-04-17 11:33:18 -03:00
canisio
cb56e78923
changed folder name for all testbench models
2026-04-17 08:31:14 -03:00
canisio
a3d46a9113
New register MF_nFrames added to PS (initialize and data genearation/capture). Not tested
2026-04-16 17:35:10 -03:00
canisio
ccc6b9cd73
Validate 16-bit Q1.15 Rx chain (baseline, partial validation)
...
Standardized ADC/DAC and channelizer input to fixdt(1,16,15)
Rescaled channelizer output from sFix25_En23 to 16-bit complex
Verified channelizer path and spectrum behavior in full simulation
Bypass path and datatype tuning (coefficients/output) pending validation
2026-04-13 17:47:08 -03:00
canisio
d4e53a67ee
Stable single frame (512 samples) baseline before capture redesign
2026-04-09 09:27:44 -03:00
canisio
520a37f520
CW mode integrated to design
2026-04-08 15:00:47 -03:00
canisio
cd91e3066b
added CW mode (with LFM) to the chirp block (TB, not integrated yet)
2026-04-08 12:19:03 -03:00
canisio
fdde9ec62b
Initiliaze funcion back to 1 (in the toggle registers). Still not working
2026-04-06 17:39:05 -03:00
canisio
ada7e324cd
Fixed register address on "update parameters"
2026-04-06 15:15:55 -03:00
canisio
7813d9744c
Modified PS part and interface towards pulse generation integration
2026-04-06 12:26:06 -03:00
canisio
872fbfcd6e
Minor changes
2026-04-01 11:51:59 -03:00
canisio
9794b2d540
tested on HW. Bypass ok.
2026-03-31 18:47:13 -03:00
canisio
b72a8cd616
added time scope to interface
2026-03-31 18:00:27 -03:00
canisio
0c6938bff2
commented initialize register on proc model
2026-03-31 17:25:01 -03:00
canisio
a9b4ad9e17
Added bypass toggle via memory mapped register
2026-03-31 16:17:34 -03:00
canisio
d8a9e026ff
Added testbench for simulink model. Added f0 option to both testbenches
2026-03-30 16:01:46 -03:00
canisio
584db6233c
- Added utilities for frequency planning
...
- Changed freq plane to: Fs 4096, int/dec 8X, Mixers 768
2026-03-27 12:50:10 -03:00
canisio
d5bbdfb435
Changed NCO on AD/DA to 0Hz. Changed language for HDL IP to Verilog. Cleaned up for new soc_prj generation
2026-03-25 18:23:42 -03:00
canisio
89c8003f5a
Added sw interface model (controls hardware running on board).
2026-03-25 17:21:09 -03:00
canisio
ac2e7bcece
Initial
2026-03-24 12:44:45 -03:00
