canisio
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beb5410390
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added visualisation to validate ouput of multiple frames
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2026-04-16 11:56:25 -03:00 |
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canisio
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eb14676581
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Oganize preload and init functions and parameters (ongoing)
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2026-04-04 15:16:58 -03:00 |
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canisio
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43f91b281b
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Tested on board. Running ok. Updated interface model and added shortcut to it.
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2026-03-27 17:52:13 -03:00 |
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canisio
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d5bbdfb435
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Changed NCO on AD/DA to 0Hz. Changed language for HDL IP to Verilog. Cleaned up for new soc_prj generation
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2026-03-25 18:23:42 -03:00 |
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canisio
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7c1292ae5c
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Added startup function to project (setup HDL tool on it)
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2026-03-25 16:15:16 -03:00 |
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canisio
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ac2e7bcece
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Initial
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2026-03-24 12:44:45 -03:00 |
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