canisio
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b72a8cd616
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added time scope to interface
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2026-03-31 18:00:27 -03:00 |
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canisio
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f66c3ffd06
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Changed interface model to reflect bypass
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2026-03-31 17:51:26 -03:00 |
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canisio
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43f91b281b
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Tested on board. Running ok. Updated interface model and added shortcut to it.
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2026-03-27 17:52:13 -03:00 |
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canisio
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7c361a9608
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Prepare to remove one of the channels. The idea is to transform the beamforming project in a simple wideband detector.
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2026-03-27 13:24:50 -03:00 |
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canisio
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584db6233c
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- Added utilities for frequency planning
- Changed freq plane to: Fs 4096, int/dec 8X, Mixers 768
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2026-03-27 12:50:10 -03:00 |
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canisio
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d5bbdfb435
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Changed NCO on AD/DA to 0Hz. Changed language for HDL IP to Verilog. Cleaned up for new soc_prj generation
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2026-03-25 18:23:42 -03:00 |
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canisio
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89c8003f5a
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Added sw interface model (controls hardware running on board).
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2026-03-25 17:21:09 -03:00 |
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