canisio
b8d2d6a5dd
updated postload funcion to not break when top is unloaded
2026-04-27 12:21:03 -03:00
canisio
4216288e2a
Removed delays from bypass
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Removed visualisation from PS
DPW visualization and log outside PS (external mode)
2026-04-27 12:09:46 -03:00
canisio
df335aac1e
validation: verified capture pipeline in counter bypass, sine bypass, and sine channelizer modes (nFrames=8)
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Validated end-to-end data integrity and visualization across all modes.
2026-04-25 12:58:22 -03:00
canisio
1ebf8aa076
codegen: increase max identifier length to 64 in soc_rfsoc_proc and gm_soc_rfsoc_top_sw
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Updated Configuration Parameters (Code Generation -> Identifiers) in both
soc_rfsoc_proc and parent model gm_soc_rfsoc_top_sw to set Maximum identifier
length from 31 to 64. This avoids truncation of generated identifiers, reduces
risk of name collisions, and ensures consistency across referenced models to
prevent build mismatches.
2026-04-25 11:53:24 -03:00
canisio
f9a2eff397
validate sine over bypass using a post processing script in the logged data. Added folter post_processing and script checkTimeSamples
2026-04-25 11:28:43 -03:00
canisio
ff3aa5e89f
Revert "Created valid_out for conter input test"
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This reverts commit a7e710b603
2026-04-24 17:25:45 -03:00
canisio
a7e710b603
Created valid_out for conter input test
2026-04-24 16:36:13 -03:00
canisio
4cbe3b5699
renamed array plots os gm model
2026-04-24 11:33:15 -03:00
canisio
bbf87121f0
changed to upper and lower halves after stream read. No difference (only first lane of 4x1 being read)
2026-04-23 15:26:22 -03:00
canisio
9a7a05f450
stream read read only first sample of [4 x 1] bundle
2026-04-22 16:38:16 -03:00
canisio
0df1044d13
Input test counter moved to Rx Subsystem
2026-04-22 14:37:28 -03:00
canisio
f5ec4e6b6e
sine and channelizer appear to work on board. Need to move counter to Rx to fully validate sample order
2026-04-22 12:29:13 -03:00
canisio
78a7d1ae68
updated interface model. Still not working
2026-04-21 10:00:38 -03:00
canisio
97d5494781
updated gm_top_sw. Runs on board, but capture is not in sync
2026-04-20 17:10:59 -03:00
canisio
7f369d8692
runs on the board. But capture is not in sync
2026-04-20 17:09:57 -03:00
canisio
040834d511
added docs folder to project path.
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tested remotely. OK
2026-04-03 20:47:13 -03:00
canisio
872fbfcd6e
Minor changes
2026-04-01 11:51:59 -03:00
canisio
9794b2d540
tested on HW. Bypass ok.
2026-03-31 18:47:13 -03:00
canisio
b72a8cd616
added time scope to interface
2026-03-31 18:00:27 -03:00
canisio
f66c3ffd06
Changed interface model to reflect bypass
2026-03-31 17:51:26 -03:00
canisio
43f91b281b
Tested on board. Running ok. Updated interface model and added shortcut to it.
2026-03-27 17:52:13 -03:00
canisio
7c361a9608
Prepare to remove one of the channels. The idea is to transform the beamforming project in a simple wideband detector.
2026-03-27 13:24:50 -03:00
canisio
584db6233c
- Added utilities for frequency planning
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- Changed freq plane to: Fs 4096, int/dec 8X, Mixers 768
2026-03-27 12:50:10 -03:00
canisio
d5bbdfb435
Changed NCO on AD/DA to 0Hz. Changed language for HDL IP to Verilog. Cleaned up for new soc_prj generation
2026-03-25 18:23:42 -03:00
canisio
89c8003f5a
Added sw interface model (controls hardware running on board).
2026-03-25 17:21:09 -03:00
