canisio
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bbf87121f0
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changed to upper and lower halves after stream read. No difference (only first lane of 4x1 being read)
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2026-04-23 15:26:22 -03:00 |
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canisio
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9a7a05f450
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stream read read only first sample of [4 x 1] bundle
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2026-04-22 16:38:16 -03:00 |
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canisio
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0df1044d13
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Input test counter moved to Rx Subsystem
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2026-04-22 14:37:28 -03:00 |
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canisio
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f5ec4e6b6e
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sine and channelizer appear to work on board. Need to move counter to Rx to fully validate sample order
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2026-04-22 12:29:13 -03:00 |
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canisio
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78a7d1ae68
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updated interface model. Still not working
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2026-04-21 10:00:38 -03:00 |
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canisio
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97d5494781
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updated gm_top_sw. Runs on board, but capture is not in sync
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2026-04-20 17:10:59 -03:00 |
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canisio
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7f369d8692
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runs on the board. But capture is not in sync
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2026-04-20 17:09:57 -03:00 |
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canisio
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040834d511
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added docs folder to project path.
tested remotely. OK
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2026-04-03 20:47:13 -03:00 |
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canisio
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872fbfcd6e
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Minor changes
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2026-04-01 11:51:59 -03:00 |
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canisio
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9794b2d540
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tested on HW. Bypass ok.
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2026-03-31 18:47:13 -03:00 |
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canisio
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b72a8cd616
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added time scope to interface
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2026-03-31 18:00:27 -03:00 |
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canisio
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f66c3ffd06
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Changed interface model to reflect bypass
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2026-03-31 17:51:26 -03:00 |
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canisio
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43f91b281b
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Tested on board. Running ok. Updated interface model and added shortcut to it.
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2026-03-27 17:52:13 -03:00 |
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canisio
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7c361a9608
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Prepare to remove one of the channels. The idea is to transform the beamforming project in a simple wideband detector.
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2026-03-27 13:24:50 -03:00 |
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canisio
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584db6233c
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- Added utilities for frequency planning
- Changed freq plane to: Fs 4096, int/dec 8X, Mixers 768
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2026-03-27 12:50:10 -03:00 |
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canisio
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d5bbdfb435
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Changed NCO on AD/DA to 0Hz. Changed language for HDL IP to Verilog. Cleaned up for new soc_prj generation
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2026-03-25 18:23:42 -03:00 |
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canisio
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89c8003f5a
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Added sw interface model (controls hardware running on board).
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2026-03-25 17:21:09 -03:00 |
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