canisio
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cd91e3066b
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added CW mode (with LFM) to the chirp block (TB, not integrated yet)
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2026-04-08 12:19:03 -03:00 |
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canisio
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fdde9ec62b
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Initiliaze funcion back to 1 (in the toggle registers). Still not working
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2026-04-06 17:39:05 -03:00 |
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canisio
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ada7e324cd
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Fixed register address on "update parameters"
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2026-04-06 15:15:55 -03:00 |
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canisio
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7813d9744c
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Modified PS part and interface towards pulse generation integration
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2026-04-06 12:26:06 -03:00 |
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canisio
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872fbfcd6e
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Minor changes
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2026-04-01 11:51:59 -03:00 |
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canisio
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9794b2d540
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tested on HW. Bypass ok.
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2026-03-31 18:47:13 -03:00 |
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canisio
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b72a8cd616
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added time scope to interface
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2026-03-31 18:00:27 -03:00 |
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canisio
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0c6938bff2
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commented initialize register on proc model
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2026-03-31 17:25:01 -03:00 |
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canisio
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a9b4ad9e17
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Added bypass toggle via memory mapped register
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2026-03-31 16:17:34 -03:00 |
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canisio
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d8a9e026ff
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Added testbench for simulink model. Added f0 option to both testbenches
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2026-03-30 16:01:46 -03:00 |
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canisio
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584db6233c
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- Added utilities for frequency planning
- Changed freq plane to: Fs 4096, int/dec 8X, Mixers 768
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2026-03-27 12:50:10 -03:00 |
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canisio
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d5bbdfb435
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Changed NCO on AD/DA to 0Hz. Changed language for HDL IP to Verilog. Cleaned up for new soc_prj generation
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2026-03-25 18:23:42 -03:00 |
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canisio
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89c8003f5a
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Added sw interface model (controls hardware running on board).
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2026-03-25 17:21:09 -03:00 |
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canisio
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ac2e7bcece
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Initial
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2026-03-24 12:44:45 -03:00 |
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