54 Commits

Author	SHA1	Message	Date
canisio	d5bbdfb435	Changed NCO on AD/DA to 0Hz. Changed language for HDL IP to Verilog. Cleaned up for new soc_prj generation	2026-03-25 18:23:42 -03:00
canisio	89c8003f5a	Added sw interface model (controls hardware running on board).	2026-03-25 17:21:09 -03:00
canisio	c86497656b	Changed fs to 1024MSPS and added double-sided spectrum visualization. FFT Shifit with two selectors and one concatenate	2026-03-24 18:10:26 -03:00
canisio	ac2e7bcece	Initial	2026-03-24 12:44:45 -03:00