canisio
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2e570cee8b
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Created folder and test bench model for new capture block. Copied from current version.
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2026-04-08 15:50:59 -03:00 |
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canisio
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ea0ecefae1
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Added documentation and updated README
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2026-04-02 17:29:24 -03:00 |
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canisio
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e810145620
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Pulse Generator TB validated
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2026-04-02 17:08:44 -03:00 |
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canisio
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790c2fdb37
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added placeholder for chirp block
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2026-04-01 12:05:57 -03:00 |
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canisio
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e0765a6afe
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Added bypass funcion and its testbench (bypass folder)
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2026-03-31 14:25:43 -03:00 |
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canisio
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7b04d52204
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Added frft functions towards codegen (c code on PS)
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2026-03-30 11:16:12 -03:00 |
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canisio
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10644b0475
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added README
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2026-03-27 18:41:29 -03:00 |
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canisio
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d5bbdfb435
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Changed NCO on AD/DA to 0Hz. Changed language for HDL IP to Verilog. Cleaned up for new soc_prj generation
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2026-03-25 18:23:42 -03:00 |
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canisio
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89c8003f5a
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Added sw interface model (controls hardware running on board).
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2026-03-25 17:21:09 -03:00 |
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canisio
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ac2e7bcece
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Initial
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2026-03-24 12:44:45 -03:00 |
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