30 Commits

Author SHA1 Message Date
canisio
05b74503dc Fixed init callback for pulse gen testbench 2026-04-06 10:45:21 -03:00
canisio
72b9a34db9 Ready to move from sine to pulse generator (Tx Subsystem) 2026-04-06 10:23:23 -03:00
canisio
3c6ae0cfe9 finished organization of init funcions and parameters 2026-04-04 16:05:17 -03:00
canisio
eb14676581 Oganize preload and init functions and parameters (ongoing) 2026-04-04 15:16:58 -03:00
canisio
040834d511 added docs folder to project path.
tested remotely. OK
2026-04-03 20:47:13 -03:00
canisio
a92709b500 Added bypass of channelizer to the documentation 2026-04-02 17:39:01 -03:00
canisio
27ec12161c detailed subsystems 2026-04-02 17:36:23 -03:00
canisio
5caaa7fd9a updated README 2026-04-02 17:32:03 -03:00
canisio
ea0ecefae1 Added documentation and updated README 2026-04-02 17:29:24 -03:00
canisio
e810145620 Pulse Generator TB validated 2026-04-02 17:08:44 -03:00
canisio
a82aed0d5a Changed NCO to complex on TBm_chirp 2026-04-02 16:43:03 -03:00
canisio
62ab58b741 Changed Update parameter subsystem on chirp TB to pulse fc and pulse BW. 2026-04-02 16:28:41 -03:00
canisio
8e397fa41e Added draft to TBm_chirp model. Added init function script to testbench 2026-04-02 12:03:59 -03:00
canisio
790c2fdb37 added placeholder for chirp block 2026-04-01 12:05:57 -03:00
canisio
872fbfcd6e Minor changes 2026-04-01 11:51:59 -03:00
canisio
9794b2d540 tested on HW. Bypass ok. 2026-03-31 18:47:13 -03:00
canisio
b72a8cd616 added time scope to interface 2026-03-31 18:00:27 -03:00
canisio
f66c3ffd06 Changed interface model to reflect bypass 2026-03-31 17:51:26 -03:00
canisio
0c6938bff2 commented initialize register on proc model 2026-03-31 17:25:01 -03:00
canisio
66ad6149e6 Added switch and led (physical) 2026-03-31 16:41:27 -03:00
canisio
a9b4ad9e17 Added bypass toggle via memory mapped register 2026-03-31 16:17:34 -03:00
canisio
0ea6881d1e Added bypass to Rx on FPGA. Test OK 2026-03-31 15:55:46 -03:00
canisio
278e318715 Added simulink model to testbench bypass funcion (bypass folder) 2026-03-31 14:26:45 -03:00
canisio
e0765a6afe Added bypass funcion and its testbench (bypass folder) 2026-03-31 14:25:43 -03:00
canisio
dd70d58f2a Added frtt_codegen folder to the project initialization 2026-03-31 09:19:28 -03:00
canisio
d8a9e026ff Added testbench for simulink model. Added f0 option to both testbenches 2026-03-30 16:01:46 -03:00
canisio
1613ae8ad9 Ran codegen for mex and tested. Working ok 2026-03-30 11:44:31 -03:00
canisio
7b04d52204 Added frft functions towards codegen (c code on PS) 2026-03-30 11:16:12 -03:00
canisio
30b31509c1 Updated README 2026-03-30 09:30:16 -03:00
canisio
10644b0475 added README 2026-03-27 18:41:29 -03:00
109 changed files with 1028 additions and 30 deletions

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# 📡 RFSoC Channelizer + PS Processing (R-ESM Prototype)
## Overview
This project is based on the RFSoC SoC Blockset reference design, adapted as a prototype for a Radar Electronic Support Measures (R-ESM) receiver.
The system implements a high-throughput signal chain in the FPGA (PL) and performs frame-based processing in the processor (PS).
---
## Current Status
- Tx subsystem: LFM pulse generator (DDS-based, complex output)
- Rx subsystem: fully functional channelizer pipeline (PFB-based)
- PL → PS interface: AXI4-Stream + DMA operational
- PS processing: frame-based algorithm (RMS + peak detection)
---
## System Architecture
ADC → Channelizer (PFB, 512 bins)
→ FFT_Capture (frame control)
→ FIFO Serializer (4 FIFOs → 1 stream)
→ AXI4-Stream (uint64)
→ DMA (S2MM)
→ PS Memory
→ Processor Algorithm
---
## Key Parameters
- ADC Sampling Rate: 4096 MSPS
- Decimation: 8
- Effective BW: 512 MHz
- Channels (FFT size): 512
- Samples per clock: 4
- FPGA clock: 128 MHz
- Frame size (PS): 512 samples
---
## 📚 Documentation
### FPGA (PL)
- [Tx Subsystem (Pulse Generator)](docs/pl_tx_subsystem.md)
- [Rx Subsystem (Channelizer)](docs/pl_rx_subsystem.md)
### Processor (PS)
- [PS Subsystem](docs/ps_subsystem.md)
---
## System Flow
Tx → Rx → PS
- Tx generates waveform
- Rx captures and channelizes
- PS processes frames
---
## Roadmap
1. Functional FrFT (PS)
2. Profiling
3. NEON optimization
4. Throughput tuning
5. PL acceleration
---
## Key Takeaway
First make it work end-to-end, then make it fast.

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# 📡 PL Rx Subsystem (Channelizer)
[🏠 Project Home](../README.md)
---
## Overview
The Rx subsystem implements a **polyphase filter bank (PFB) channelizer** followed by FFT processing.
It converts wideband ADC input into frequency-domain channels and streams the result to the PS.
A **bypass path** is also available for raw data inspection and debugging.
---
## Architecture
### Channelizer Path (default)
ADC
PFB Channelizer (Decimation + Filtering)
FFT (512 bins)
FFT Capture
FIFO Serializer (4 → 1)
AXI4-Stream
DMA
---
### Bypass Path (Debug / Raw Data)
ADC
Bypass Path
FIFO / Serializer
AXI4-Stream
DMA
---
## Bypass Functionality
The bypass allows direct observation of the input signal without channelization.
### Purpose
- Debugging and validation
- Access to raw ADC-domain data
- Comparison with channelized output
- Verification of downstream processing
---
### Behavior
- Input data is routed directly to output
- No filtering or FFT applied
- Maintains same output interface (AXI4-Stream)
---
### Selection Mechanism
A selector signal chooses between:
- Channelizer output (normal operation)
- Bypass output (raw data)
Implementation typically uses:
- Parallel paths
- Output switching logic
---
## Processing Chain (Channelizer Mode)
### ADC Input
- Sampling rate: 4096 MSPS
### PFB Channelizer
- Decimation: 8
- Effective bandwidth: 512 MHz
### FFT
- Size: 512
- Produces frequency bins
### FFT Capture
- Controls frame boundaries
### FIFO Serializer
- Converts parallel streams into single stream
---
## AXI4-Stream Output
- Data type: uint64
- Packed real/imag
- TLAST = frame boundary
---
## Data Format
- Frame size: 512 samples
- Complex values packed into uint64
---
## Key Characteristics
- Fully streaming pipeline
- High throughput
- Deterministic latency
- Supports dual-mode operation (channelizer / bypass)
---
## 🔗 Related Components
- [🏠 Project Home](../README.md)
- [PL Tx Subsystem](pl_tx_subsystem.md)
- [PS Subsystem](ps_subsystem.md)

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# 📡 PL Tx Subsystem (Pulse Generator)
[🏠 Project Home](../README.md)
---
## Overview
The Tx subsystem implements a **pulse-based Linear Frequency Modulated (LFM) chirp generator** using a DDS/NCO architecture in the FPGA (PL).
The generator produces **complex baseband output**:
x[n] = exp(j·φ[n])
and operates deterministically in the PL after a trigger from the PS.
---
## Architecture
TxPulseStart (PS)
pulse_gen_ctrl (FSM)
tx_active
Phase Increment Counter
NCO (DDS)
Complex Output (I/Q)
---
## Chirp Generation Principle
The chirp is generated using a second-order phase accumulator:
Δφ[n] = Δφ[n1] + step
φ[n] = φ[n1] + Δφ[n]
This results in a linear frequency sweep.
---
## Parameterization (PS → PL)
Inputs:
- Center frequency: Fc
- Bandwidth: B
- Pulse width: N (samples)
Derived internally:
f_start = Fc B/2
step = B / (N 1)
These values are converted to DDS phase increments before being written to PL registers.
---
## Pulse Timing (FSM)
States:
- IDLE: waits for trigger and latches parameters
- ACTIVE: generates pulses
- DONE: waits for trigger reset
---
## Timing Behavior
Within each PRI:
|<------ PRI ------>|
|<-- pulse -->| idle |
- tx_active = 1 → chirp output
- tx_active = 0 → output zero
Chirp is reset at each pulse start.
---
## Burst Trigger (PS Interaction)
- Controlled via TxPulseStart (memory-mapped register)
- Rising edge triggers burst
- PL runs autonomously afterward
---
## Key Characteristics
- Deterministic timing (128 MHz)
- Efficient DDS (adder-based)
- Complex output (I/Q)
- Supports burst-mode radar operation
---
## 🔗 Related Components
- [🏠 Project Home](../README.md)
- [PL Rx Subsystem](pl_rx_subsystem.md)
- [PS Subsystem](ps_subsystem.md)

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# 🧠 PS Subsystem (Control + Processing)
[🏠 Project Home](../README.md)
---
## Overview
The PS subsystem is responsible for:
- Configuring PL subsystems
- Receiving data via DMA
- Performing frame-based processing
---
## Responsibilities
### Control
- Writes parameters to PL registers:
- Tx generator configuration
- Generates TxPulseStart trigger
---
### DMA Handling
- AXI4-Stream → DMA (S2MM)
- Data stored in PS DDR
Configuration:
- Frame size: 512
- Buffers: 16
---
### Processing Pipeline
DMA → uint64[512]
→ unpack real/imag
→ convert to complex
→ RMS + peak detection
---
## Execution Model
- Event-driven (DMA trigger)
- No buffering queue
- Frames may be dropped
---
## Performance Notes
- Bottleneck: unpacking + conversion
- Cannot sustain full-rate input
---
## Interaction with PL
### Tx Control
- Low-rate trigger (~Hz)
- Starts burst generation
### Rx Data
- Continuous high-rate stream
---
## Future Work
- Replace processing with FrFT
- NEON optimization
- Throughput improvements
---
## 🔗 Related Components
- [🏠 Project Home](../README.md)
- [PL Tx Subsystem](pl_tx_subsystem.md)
- [PL Rx Subsystem](pl_rx_subsystem.md)

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%% FrFT Validation Script (Reference vs Original)
% Author: Canisio Barth
clear; clc; close all;
%% Parameters
Fs = 512e6; % Sampling rate
T = 1e-6; % Signal duration
N = Fs*T; % 512 samples
n = (0:N-1).';
t = (n - N/2)/ Fs;
% Beta range (Hz/s)
betas = (-32e12 : 8e12 : 32e12);
% Order sweep (for heatmap)
a_vec = linspace( 0.5, 1.5, 100);
% Center frequency
f0 = 0e6; % center frequency (Hz) set as needed
%% ============================================================
%% A) HEATMAP (single chirp, order sweep)
%% ============================================================
beta0 = 64e12; % pick one chirp for visualization
% Generate LFM chirp
x = exp(1j*(2*pi*f0*t + pi*beta0*t.^2));
% External interpolation (IMPORTANT)
x_interp = bizinter(x);
N_interp = length(x_interp);
N_out = N_interp/2; % after decimation
% Allocate
FrFT_map_ref = zeros(N_out, length(a_vec));
FrFT_map_cmp = zeros(N_out, length(a_vec));
for k = 1:length(a_vec)
a = a_vec(k);
% Reference
y_ref = fracF_ref(x_interp, a);
%y_ref = fracF_cg(x_interp, a);
% Comparison (original / other implementation)
%y_cmp = fracF_cg(x_interp, a);
y_cmp = fracF_cg_mex(single(x_interp), single(a));
FrFT_map_ref(:,k) = y_ref;
FrFT_map_cmp(:,k) = double(y_cmp);
end
% Global relative error
rel_err_global = norm(FrFT_map_ref(:) - FrFT_map_cmp(:)) / ...
norm(FrFT_map_ref(:));
fprintf('Global relative error: %.3e\n', rel_err_global);
% Plot - Reference
figure;
imagesc(a_vec, -N_out/2:N_out/2-1, abs(FrFT_map_ref) / sqrt(N));
axis xy;
xlabel('Order a');
ylabel('Index');
title('FrFT Magnitude (Reference)');
colorbar;
% Plot - Comparison
figure;
imagesc(a_vec, -N_out/2:N_out/2-1, abs(FrFT_map_cmp) / sqrt(N));
axis xy;
xlabel('Order a');
ylabel('Index');
title('FrFT Magnitude (Comparison)');
colorbar;
% Plot - Difference
figure;
rel_err_map = abs(FrFT_map_ref - FrFT_map_cmp) ./ ...
(abs(FrFT_map_ref) + eps);
imagesc(a_vec, -N_out/2:N_out/2-1, rel_err_map);
axis xy;
xlabel('Order a');
ylabel('Index');
title('Absolute Difference |Ref - Cmp|');
colorbar;
%% ============================================================
%% B) PEAK VS BETA (matched order)
%% ============================================================
peak_ref = zeros(size(betas));
peak_cmp = zeros(size(betas));
for i = 1:length(betas)
beta = betas(i);
% Generate chirp
x = exp(1j*(2*pi*f0*t + pi*beta*t.^2));
% External interpolation
x_interp = bizinter(x);
% Matched order
a = -(2/pi)*atan(Fs/(beta*T));
% Compute FrFT
y_ref = fracF_ref(x_interp, a);
%y_ref = fracF_cg(x_interp, a);
%y_cmp = fracF_cg(x_interp, a);
y_cmp = fracF_cg_mex(single(x_interp), single(a));
% Normalized peak magnitude
peak_ref(i) = max(abs(y_ref)) / sqrt(N);
peak_cmp(i) = max(abs(y_cmp)) / sqrt(N);
end
% Plot peaks
figure;
plot(betas/1e12, peak_ref, 'o-', 'LineWidth', 1.5); hold on;
plot(betas/1e12, peak_cmp, 's--', 'LineWidth', 1.5);
xlabel('\beta (MHz/\mus)');
ylabel('Peak Magnitude');
title('Peak vs Chirp Rate');
legend('Reference','Comparison');
grid on;
% Plot relative error
figure;
rel_err = abs(peak_ref - peak_cmp) ./ peak_ref;
plot(betas/1e12, rel_err, 'o-', 'LineWidth', 1.5);
xlabel('\beta (MHz/\mus)');
ylabel('Relative Error');
title('Relative Error between Implementations');
grid on;

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function xint=bizinter(x)
N=length(x);
im = 0;
if sum(abs(imag(x)))>0
im = 1;
imx = imag(x);
x = real(x);
end
x2=x(:);
x2=[x2.'; zeros(1,N)];
x2=x2(:);
xf=fft(x2);
if rem(N,2)==1 %N = odd
N1=fix(N/2+1); N2=2*N-fix(N/2)+1;
xint=2*real(ifft([xf(1:N1); zeros(N,1) ;xf(N2:2*N)].'));
else
xint=2*real(ifft([xf(1:N/2); zeros(N,1) ;xf(2*N-N/2+1:2*N)].'));
end
if ( im == 1)
x2=imx(:);
x2=[x2.'; zeros(1,N)];
x2=x2(:);
xf=fft(x2);
if rem(N,2)==1 %N = odd
N1=fix(N/2+1); N2=2*N-fix(N/2)+1;
xmint=2*real(ifft([xf(1:N1); zeros(N,1) ;xf(N2:2*N)].'));
else
xmint=2*real(ifft([xf(1:N/2); zeros(N,1) ;xf(2*N-N/2+1:2*N)].'));
end
xint = xint + 1j*xmint;
end
xint = xint(:);
end

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function F = fracF_cg(f, a)
%#codegen
%% fracF_cg Fractional Fourier Transform (FrFT) - codegen-ready version
%
% Author: Canisio Barth
%
% F = fracF_cg(f, a) computes the Fractional Fourier Transform (FrFT)
% of the input signal 'f' for a single transform order 'a'.
%
% This version is adapted for MATLAB Coder and hardware-oriented workflows.
%
% Key characteristics:
% - Fixed input size: [1024 x 1] complex(single)
% - Output size: [512 x 1] complex(single)
% - Assumes input 'f' is already interpolated externally
% - No input validation (assumes valid scalar 'a' in core region)
% - Deterministic execution (no branching, no dynamic allocation)
%
% INPUTS:
% f - [1024 x 1] complex(single)
% a - scalar single
%
% OUTPUTS:
% F - [512 x 1] complex(single)
%
% Notes:
% - Internal FFT size = 2048
% - Designed for code generation and future FPGA mapping
% Fixed sizes
N = 1024;
%N2 = 512;
Nfft = 2048;
% Ensure types
pi_s = single(pi);
% Transform parameter
phi = a * (pi_s / 2);
% Precompute trig terms
tan_half_phi = tan(phi / 2);
sin_phi = sin(phi);
cos_phi = cos(phi);
csc_phi = 1 / sin_phi;
cot_phi = cos_phi / sin_phi;
twoDelta = 2 * sqrt(single(N) / 2);
%% === Chirp A ===
n = single((-N/2:N/2-1).') / twoDelta;
Achirp = exp(-1j * pi_s * (n .* n) * tan_half_phi);
%% Chirp multiplication #1
g = Achirp .* f;
%% === Chirp B ===
m = single((-N:N-1).') / twoDelta;
Bchirp = exp(1j * pi_s * csc_phi .* (m .* m));
%% === Zero-padded buffer ===
g_pad = complex(zeros(Nfft,1,'single'));
g_pad(1:N) = g;
%% === FFT convolution ===
G = ifft( fft(g_pad) .* fft(Bchirp) );
%% Extract valid part and decimate
G_valid = G(N+1:2:end); % [512 x 1]
%% Complex phase constant
Aphi = sqrt(1 - 1j * cot_phi);
%% === Chirp multiplication #2 ===
F = (Aphi / twoDelta) .* G_valid .* Achirp(1:2:end);
end

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function [F] = fracF_ref(f, a)
%% fracF_ref Reference Fractional Fourier Transform (FrFT) implementation
%
% Author: Canisio Barth
%
% F = fracF_ref(f, a) computes the Fractional Fourier Transform (FrFT)
% of the input signal 'f' for a single transform order 'a'.
%
% This function serves as a reference (golden model) for validation and
% comparison against future code generation and hardware-oriented
% implementations.
%
% Key characteristics:
% - Scalar transform order 'a' (no vector support).
% - Assumes input signal 'f' is already interpolated externally.
% - Maintains original algorithm structure, including internal
% decimation after convolution.
% - Uses full MATLAB flexibility (not yet restricted for codegen).
%
% INPUTS:
% f - Input signal, [N x 1] column vector.
% IMPORTANT: 'f' must already be interpolated (expanded signal).
%
% a - Scalar transform order.
% Expected to satisfy: 0.5 < |a| < 1.5
%
% OUTPUTS:
% F - Fractional Fourier Transform, [(N/2) x 1] column vector.
% (Decimated output, consistent with original algorithm.)
%
% LIMITATIONS:
% - No internal interpolation is performed.
% - Only valid for scalar 'a'.
% - Assumes caller enforces correct parameter range and signal format.
%
% See also: fracF (Ozaktas)
% Validate scalar 'a'
if ~isscalar(a)
error('Parameter ''a'' must be scalar.');
end
% Range check (core region)
if abs(a) < 0.5 || abs(a) > 1.5
error('Parameter ''a'' must be within the interval [0.5, 1.5].');
end
N = length(f); % already interpolated length
% Transform parameter
twoDelta = 2 * sqrt(N/2);
phi = a * pi / 2;
% === Chirp A ===
n = ((-N/2:N/2-1) / twoDelta).';
Achirp = exp(-1j * pi * (n .* n) * tan(phi/2));
% Chirp multiplication #1
g = Achirp .* f;
% === Chirp B ===
m = ((-N:N-1) / twoDelta).';
Bchirp = exp(1j * pi * csc(phi) .* (m .* m));
% === Chirp convolution ===
G = ifft(fft([g; zeros(N,1)]) .* fft(Bchirp));
% Extract valid part and decimate
G = G(end/2+1:2:end);
% Complex phase constant
Aphi = sqrt(1 - 1j * cot(phi));
% === Chirp multiplication #2 ===
F = (Aphi / twoDelta) .* G .* Achirp(1:2:end);
end

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<?xml version="1.0" encoding="UTF-8"?>
<Info location="TBc_lfm_fracF.m" type="File"/>

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<?xml version="1.0" encoding="UTF-8"?>
<Info location="fracF_cg.m" type="File"/>

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<Info/>

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<?xml version="1.0" encoding="UTF-8"?>
<Info location="1" type="DIR_SIGNIFIER"/>

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<?xml version="1.0" encoding="UTF-8"?>
<Info location="bizinter.m" type="File"/>

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<?xml version="1.0" encoding="UTF-8"?>
<Info location="fracF_ref.m" type="File"/>

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<?xml version="1.0" encoding="UTF-8"?>
<Info location="TBm_lfm_fracF.slx" type="File"/>

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<?xml version="1.0" encoding="UTF-8"?>
<Info/>

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<?xml version="1.0" encoding="UTF-8"?>
<Info location="aux" type="File"/>

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<?xml version="1.0" encoding="UTF-8"?>
<Info location="soc_rfsoc_prj_startup.m" type="File"/>

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<?xml version="1.0" encoding="UTF-8"?>
<Info location="soc_rfsoc_preload.m" type="File"/>

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<?xml version="1.0" encoding="UTF-8"?>
<Info location="soc_rfsoc_startup.m" type="File"/>

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<?xml version="1.0" encoding="UTF-8"?>
<Info>
<Category UUID="FileClassCategory">
<Label UUID="design"/>
</Category>
</Info>

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<?xml version="1.0" encoding="UTF-8"?>
<Info location="soc_rfsoc_postload.m" type="File"/>

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<?xml version='1.0' encoding='UTF-8'?>
<Info Ref="" Type="Relative"/>

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<?xml version='1.0' encoding='UTF-8'?>
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<?xml version="1.0" encoding="UTF-8"?>
<Info Ref="bypass_block" Type="Relative"/>

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