NEON optimization enabled for C code generation on both proc and interface models

Formatted top diagrams

README.md

@@ -11,22 +11,35 @@ The system implements a high-throughput signal chain in the FPGA (PL) and perfor
 ## Current Status
 
 - Tx subsystem: LFM pulse generator (DDS-based, complex output)
-- Rx subsystem: fully functional channelizer pipeline (PFB-based)
+- Rx subsystem: fully functional channelizer pipeline (PFB-based) or bypass
 - PL → PS interface: AXI4-Stream + DMA operational
-- PS processing: frame-based algorithm (RMS + peak detection)
+- PS processing: frame-based algorithm on a Data Process Window (DPW)
 
 ---
 
 ## System Architecture
 
-ADC → Channelizer (PFB, 512 bins)  
+Tx (PL)  
-→ FFT_Capture (frame control)  
+→ Waveform Generator (LFM / CW / Pulsed)  
-→ FIFO Serializer (4 FIFOs → 1 stream)  
+→ DAC  
-→ AXI4-Stream (uint64)  
+→ RF Loopback / Input  
+
+Rx (PL)   
+→ ADC  
+→ Channelizer (PFB, 512 bins) / Bypass / Counter  
+→ Capture (frame control)  
+→ AXI4-Stream (128-bit, 4 samples/clock)  
 → DMA (S2MM)  
 → PS Memory  
 → Processor Algorithm
 
+Post Processing (PS)  
+→ Triggered Capture  
+→ Sample Unpacking (I/Q)  
+→ Data Reshaping → [FrameSize x nFrames x nTriggers]  
+→ Host Communication / Processing / Visualization
+→ One DPW is a windows of FrameSize x nFrames samples
+
 ---
 
 ## Key Parameters

codegen_frft/TBc_lfm_fracF.m

@@ -1,4 +1,4 @@
-%% FrFT Validation Script (Reference vs Original)
+  %% FrFT Validation Script (Reference vs Original)
 % Author: Canisio Barth
 
 clear; clc; close all;

docs/pl_rx_subsystem.md

@@ -6,11 +6,9 @@
 
 ## Overview
 
-The Rx subsystem implements a **polyphase filter bank (PFB) channelizer** followed by FFT processing.
+The Rx subsystem implements a **polyphase filter bank (PFB) channelizer** followed by FFT processing, a **bypass path**, and a **multi-frame capture pipeline**.
 
-It converts wideband ADC input into frequency-domain channels and streams the result to the PS.
+It converts wideband ADC input into frequency-domain channels (or raw samples via bypass) and streams the result to the PS.
-
-A **bypass path** is also available for raw data inspection and debugging.
 
 ---
 
@@ -24,11 +22,9 @@ PFB Channelizer (Decimation + Filtering)
  ↓  
 FFT (512 bins)  
  ↓  
-FFT Capture
+Capture (frame control)  
  ↓  
-FIFO Serializer (4 → 1)
+AXI4-Stream (128-bit, 4 samples/clock)  
- ↓
-AXI4-Stream
  ↓  
 DMA
 
@@ -40,45 +36,26 @@ ADC
  ↓  
 Bypass Path  
  ↓  
-FIFO / Serializer
+Capture (frame control)  
  ↓  
-AXI4-Stream
+AXI4-Stream (128-bit, 4 samples/clock)  
  ↓  
 DMA
 
 ---
 
-## Bypass Functionality
+## Capture Pipeline
 
-The bypass allows direct observation of the input signal without channelization.
+- Multi-frame acquisition (configurable nFrames)
-
+- Frame size: 512 samples
-### Purpose
+- Supports asynchronous capture start (not frame-aligned)
-
+- TLAST asserted at frame boundaries
-- Debugging and validation
-- Access to raw ADC-domain data
-- Comparison with channelized output
-- Verification of downstream processing
-
----
 
 ### Behavior
 
-- Input data is routed directly to output
+- First frame may be partial
-- No filtering or FFT applied
+- Frames may contain ≤ 2 frame indices (expected)
-- Maintains same output interface (AXI4-Stream)
+- DPW spans nFrames frames but covers nFrames + 1 frame regions
-
----
-
-### Selection Mechanism
-
-A selector signal chooses between:
-
-- Channelizer output (normal operation)
-- Bypass output (raw data)
-
-Implementation typically uses:
-- Parallel paths
-- Output switching logic
 
 ---
 
@@ -86,6 +63,7 @@ Implementation typically uses:
 
 ### ADC Input
 - Sampling rate: 4096 MSPS
+- Data type: **fixdt(1,16,15)** (Q1.15)
 
 ### PFB Channelizer
 - Decimation: 8
@@ -95,35 +73,67 @@ Implementation typically uses:
 - Size: 512
 - Produces frequency bins
 
-### FFT Capture
+### Capture
-- Controls frame boundaries
+- Defines frame boundaries (512 samples)
+- Generates TLAST
 
-### FIFO Serializer
+---
-- Converts parallel streams into single stream
+
+## Numeric Format and Scaling
+
+### System Standardization
+
+- End-to-end Q1.15 (**fixdt(1,16,15)**)
+
+### Channelizer Output Scaling
+
+- Native: **sFix25_En23**
+- Quantized to: **fixdt(1,16,15)** (round + saturate)
+
+---
+
+## Data Packing (Updated)
+
+- 4 samples per clock
+- Each sample: complex (16-bit real + 16-bit imag)
+- Packed into **128-bit AXI4-Stream word**
+
+Benefits:
+- Matches datapath parallelism
+- Efficient DMA transfers
+- Eliminates need for serializer stage
 
 ---
 
 ## AXI4-Stream Output
 
-- Data type: uint64
+- Width: 128 bits
-- Packed real/imag
+- Contains 4 complex samples per cycle
 - TLAST = frame boundary
 
 ---
 
-## Data Format
+## Debug / Validation Features
 
-- Frame size: 512 samples
+A counter-based debug mode is implemented:
-- Complex values packed into uint64
+
+- Real part → sample counter (0..511)
+- Imag part → frame index
+
+Used to validate:
+- Sample continuity
+- Frame boundaries
+- DMA ordering and integrity
 
 ---
 
 ## Key Characteristics
 
 - Fully streaming pipeline
-- High throughput
 - Deterministic latency
-- Supports dual-mode operation (channelizer / bypass)
+- High throughput (4 samples/clock)
+- Dual-mode operation (channelizer / bypass)
+- Validated up to nFrames = 1024
 
 ---
 

docs/pl_tx_subsystem.md

@@ -1,4 +1,4 @@
-# 📡 PL Tx Subsystem (Pulse Generator)
+# 📡 PL Tx Subsystem (Pulse & Continuous LFM Generator)
 
 [🏠 Project Home](../README.md)
 
@@ -6,7 +6,7 @@
 
 ## Overview
 
-The Tx subsystem implements a **pulse-based Linear Frequency Modulated (LFM) chirp generator** using a DDS/NCO architecture in the FPGA (PL).
+The Tx subsystem implements a **pulse-based and continuous Linear Frequency Modulated (LFM) chirp generator** using a DDS/NCO architecture in the FPGA (PL).
 
 The generator produces **complex baseband output**:
 
@@ -24,7 +24,7 @@ pulse_gen_ctrl (FSM)
         ↓  
    tx_active  
         ↓  
-Phase Increment Counter
+Phase Increment Logic  
         ↓  
       NCO (DDS)  
         ↓  
@@ -32,6 +32,39 @@ Phase Increment Counter
 
 ---
 
+## Operating Modes
+
+The subsystem now supports multiple Tx modes:
+
+### 1. Pulsed LFM (default)
+
+- Chirp generated only during pulse window
+- Phase resets at each pulse start
+- Standard radar burst operation
+
+---
+
+### 2. CW Mode (Continuous Wave)
+
+- `tx_active = 1` continuously
+- Generates a single-tone output
+- Achieved by setting constant phase increment
+
+---
+
+### 3. Continuous LFM (Workaround Implementation)
+
+- `tx_active` forced HIGH continuously  
+- A **1-cycle LOW pulse** is inserted periodically  
+- This LOW→HIGH transition **resets the NCO**
+
+Result:
+- Continuous chirp
+- Bounded bandwidth
+- Periodic repetition of LFM
+
+---
+
 ## Chirp Generation Principle
 
 The chirp is generated using a second-order phase accumulator:
@@ -72,7 +105,7 @@ States:
 
 ## Timing Behavior
 
-Within each PRI:
+### Pulsed Mode
 
 |<------ PRI ------>|
 |<-- pulse -->| idle |
@@ -80,7 +113,31 @@ Within each PRI:
 - tx_active = 1 → chirp output  
 - tx_active = 0 → output zero  
 
-Chirp is reset at each pulse start.
+---
+
+### Continuous LFM Mode
+
+tx_active behavior:
+
+1 1 1 1 1 0 1 1 1 1 ...
+
+- 1-cycle LOW inserted at end of chirp period  
+- Rising edge resets NCO  
+- Defines chirp repetition interval  
+
+---
+
+## CW / Continuous LFM Implementation Details
+
+- CW mode bypasses FSM output
+- A dedicated counter generates periodic reset pulses
+- Reset timing is based on `pulse_width_cycles`
+
+Important:
+
+- Reset pulse is exactly **1 clock cycle**
+- Ensures deterministic NCO restart
+- Decoupled from PRI/FSM timing
 
 ---
 
@@ -97,7 +154,19 @@ Chirp is reset at each pulse start.
 - Deterministic timing (128 MHz)
 - Efficient DDS (adder-based)
 - Complex output (I/Q)
-- Supports burst-mode radar operation
+- Supports:
+  - Pulsed radar mode
+  - Continuous wave (CW)
+  - Continuous LFM (periodic chirp)
+
+---
+
+## Design Notes
+
+- FSM controls **timing (when to transmit)**
+- NCO controls **frequency evolution**
+- Continuous LFM implemented via **tx_active edge reuse**
+- Minimal hardware overhead (no additional NCO logic)
 
 ---
 

docs/ps_subsystem.md

@@ -1,4 +1,4 @@
-# 🧠 PS Subsystem (Control + Processing)
+# 🧠 PS Subsystem (Control + Capture + Processing)
 
 [🏠 Project Home](../README.md)
 
@@ -8,73 +8,128 @@
 
 The PS subsystem is responsible for:
 
+- System initialization
 - Configuring PL subsystems
+- Triggering captures
 - Receiving data via DMA
-- Performing frame-based processing
+- Preparing data for processing and visualization
+
+The current implementation acts as a **placeholder for post-processing**, focusing on reliable data acquisition and host interaction.
 
 ---
 
 ## Responsibilities
 
-### Control
+### Control & Initialization
 
-- Writes parameters to PL registers:
+- Configure PL parameters:
-  - Tx generator configuration
+  - Tx waveform configuration
-- Generates TxPulseStart trigger
+  - Capture parameters (nFrames, etc.)
+- Initialize DMA and memory buffers
+- Manage system startup
+
+---
+
+### Trigger & Capture
+
+- Generates capture trigger (software-controlled)
+- Controls DPW acquisition timing
+- Each trigger initiates one DPW capture
 
 ---
 
 ### DMA Handling
 
 - AXI4-Stream → DMA (S2MM)
-- Data stored in PS DDR
+- Receives **128-bit stream** (4 samples per clock)
+- Stores data in PS DDR memory
 
 Configuration:
-- Frame size: 512
+- Frame size: 512 samples
-- Buffers: 16
+- nFrames: configurable (validated up to 1024)
 
 ---
 
-### Processing Pipeline
+## Data Format
 
-DMA → uint64[512]  
+### Raw DMA Data
-→ unpack real/imag  
+
-→ convert to complex  
+- Packed complex samples
-→ RMS + peak detection  
+- 16-bit real + 16-bit imag per sample
+- 4 samples per 128-bit word
+
+---
+
+### Processing Representation
+
+Data is unpacked and reshaped into:
+
+```
+[FrameSize x nFrames x nTriggers]
+```
+
+---
+
+## Processing Pipeline (Current)
+
+DMA  
+→ Unpack samples (I/Q separation)  
+→ Convert to complex representation  
+→ Reshape into 3D structure  
+→ Visualization / basic analysis  
+
+---
+
+## Validation Support
+
+Uses counter-based validation:
+
+- Real part → sample counter
+- Imag part → frame index
+
+Enables verification of:
+
+- Data continuity
+- Frame alignment
+- Correct ordering from DMA
 
 ---
 
 ## Execution Model
 
-- Event-driven (DMA trigger)
+- Triggered (event-based)
-- No buffering queue
+- Burst capture (DPW)
-- Frames may be dropped
+- Not continuous real-time streaming
 
 ---
 
 ## Performance Notes
 
-- Bottleneck: unpacking + conversion
+- Designed for correctness and validation (not optimized)
-- Cannot sustain full-rate input
+- Bottleneck: unpacking + data movement
+- Full-rate continuous processing not supported
 
 ---
 
-## Interaction with PL
+## Role in System
 
-### Tx Control
+The PS currently serves as:
-- Low-rate trigger (~Hz)
-- Starts burst generation
 
-### Rx Data
+- Control interface
-- Continuous high-rate stream
+- Data acquisition manager
+- Pre-processing stage
+
+Future implementations will replace the current processing with advanced algorithms (e.g., FrFT).
 
 ---
 
 ## Future Work
 
-- Replace processing with FrFT
+- FrFT-based processing
-- NEON optimization
+- Timestamp integration
-- Throughput improvements
+- UDP streaming
+- Optimization (NEON / vectorization)
+- Metadata extraction (move complexity to PL)
 
 ---
 

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-<?xml version="1.0" encoding="UTF-8"?>
-<Info location="pulsegen_block" type="File"/>

resources/project/qaw0eS1zuuY1ar9TdPn1GMfrjbQ/QuVfFK49N05REJIAYZLQasz_VuMd.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info/>

resources/project/qaw0eS1zuuY1ar9TdPn1GMfrjbQ/QuVfFK49N05REJIAYZLQasz_VuMp.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="block_capture" type="File"/>

resources/project/qaw0eS1zuuY1ar9TdPn1GMfrjbQ/bMFzsIHr-EVKQIO2sqeU-274_I8d.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info/>

resources/project/qaw0eS1zuuY1ar9TdPn1GMfrjbQ/bMFzsIHr-EVKQIO2sqeU-274_I8p.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="block_bypass" type="File"/>

utilities/post_processing/checkCounterSamples.m

@@ -0,0 +1,116 @@
+%% =========================================================
+%  Data
+% =========================================================
+clc;
+X = raw_DPW.Data;   % [512 x nFrames x nTime]
+
+% Remove first DPW if needed (initialization artifact)
+X = X(:,:,2:end);
+
+[nSamples, nFrames_cfg, nTime] = size(X);
+
+%% =========================================================
+%  PARAMETERS
+% =========================================================
+COUNTER_MAX = 511;     % counter: 0..511
+
+%% =========================================================
+%  VALIDATION
+% =========================================================
+for t = 1:nTime
+
+    fprintf('\n=== Checking DPW %d ===\n', t);
+
+    X_dpw = X(:,:,t);
+
+    % Flatten stream
+    x_seq = reshape(X_dpw, [], 1);
+
+    % Extract stored integers
+    real_seq  = double(storedInteger(real(x_seq)));  % sample counter
+    frame_seq = double(storedInteger(imag(x_seq)));  % frame index
+
+    %% -----------------------------------------------------
+    % 1. Sample progression
+    % -----------------------------------------------------
+    d_real = diff(real_seq);
+
+    valid_steps = (d_real == 1) | (d_real == -COUNTER_MAX);
+
+    if all(valid_steps)
+        fprintf('✔ Sample progression OK\n');
+    else
+        idx = find(~valid_steps, 1);
+        fprintf('❌ Sample progression ERROR at index %d\n', idx);
+    end
+
+    %% -----------------------------------------------------
+    % 2. Detect counter wraps (511 → 0)
+    % -----------------------------------------------------
+    wrap_idx = find(real_seq(1:end-1) == COUNTER_MAX & real_seq(2:end) == 0);
+
+    fprintf('Detected wraps: %d (configured: %d)\n', ...
+        length(wrap_idx), nFrames_cfg);
+
+    if length(wrap_idx) == nFrames_cfg
+        fprintf('✔ Wrap count matches configuration\n');
+    else
+        fprintf('❌ Wrap count mismatch\n');
+    end
+
+    %% -----------------------------------------------------
+    % 3. Check frame increment at wraps (no wrap logic)
+    % -----------------------------------------------------
+    ok_wrap = true;
+
+    for k = 1:length(wrap_idx)
+
+        i = wrap_idx(k);
+
+        f_before = frame_seq(i);
+        f_after  = frame_seq(i+1);
+
+        if f_after ~= f_before + 1
+            fprintf('❌ Frame increment error at idx %d (%d → %d)\n', ...
+                i, f_before, f_after);
+            ok_wrap = false;
+            break;
+        end
+
+    end
+
+    if ok_wrap
+        fprintf('✔ Frame increments correctly at all wraps\n');
+    end
+
+    %% -----------------------------------------------------
+    % 4. Informative: frame regions (+1 effect)
+    % -----------------------------------------------------
+    d_frame = diff(frame_seq);
+    nFrames_detected = sum(d_frame == 1) + 1;
+
+    fprintf('Frame regions (including partial): %d (expected: %d + 1)\n', ...
+        nFrames_detected, nFrames_cfg);
+
+    %% -----------------------------------------------------
+    % 5. Optional: per-frame sanity (≤2 indices)
+    % -----------------------------------------------------
+    frame_idx_matrix = storedInteger(imag(X_dpw));
+
+    frame_ok = true;
+
+    for f = 1:nFrames_cfg
+        u = unique(frame_idx_matrix(:,f));
+
+        if length(u) > 2
+            fprintf('❌ Frame %d has >2 frame indices\n', f);
+            frame_ok = false;
+            break;
+        end
+    end
+
+    if frame_ok
+        fprintf('✔ Frame structure OK (≤2 indices per frame)\n');
+    end
+
+end

utilities/post_processing/checkFreqSamples.m

@@ -0,0 +1,87 @@
+%% =========================================================
+%  Data
+% =========================================================
+X = single(raw_DPW.Data);   % [512 x nFrames x nTime]
+X = X(:,:,2:end);           % First DPW is zeroed
+X = 2*X;                    % Rescale (see channelizer block on PL)
+
+[nSamples, nFrames, nTime] = size(X);
+N  = nSamples;
+
+%% =========================================================
+%  Parameters
+% =========================================================
+Fs = 512e6; % Hz
+
+f_axis = (-N/2 : N/2-1) * (Fs/N) / 1e6; % MHz
+
+%% =========================================================
+%  Apply fftshift per frame (dim = 1)
+% =========================================================
+X_shift = fftshift(X, 1);
+
+%% =========================================================
+%  Convert to power
+% =========================================================
+P = abs(X_shift).^2;
+
+%% =========================================================
+%  OPTION 1 — Mean Spectrum (over frames AND time)
+% =========================================================
+P_mean = mean(P, [2 3]);   % average over frames and triggers
+P_mean = squeeze(P_mean);  % [512 x 1]
+
+figure;
+plot(f_axis, 10*log10(P_mean + 1e-12), 'LineWidth', 1.5);
+grid on;
+
+xlabel('Frequency (MHz)');
+ylabel('Power (dB)');
+title('Mean Channelized Spectrum (Frames + Time)');
+
+%% =========================================================
+%  OPTION 2 — Max Spectrum (detect intermittent peaks)
+% =========================================================
+P_max = max(P, [], [2 3]);
+P_max = squeeze(P_max);
+
+figure;
+plot(f_axis, 10*log10(P_max + 1e-12), 'LineWidth', 1.5);
+grid on;
+
+xlabel('Frequency (MHz)');
+ylabel('Power (dB)');
+title('Max Channelized Spectrum (Frames + Time)');
+
+%% =========================================================
+%  OPTION 3 — Time-Frequency Visualization
+% =========================================================
+% Collapse frames → keep time evolution
+P_time = squeeze(mean(P, 2));   % [512 x nTime]
+
+figure;
+surf(1:nTime, f_axis, 10*log10(P_time + 1e-12), 'EdgeColor','none');
+view(2);
+axis tight;
+
+xlabel('Trigger Index');
+ylabel('Frequency (MHz)');
+title('Channelizer Output Over Time');
+colorbar;
+
+%% =========================================================
+%  OPTIONAL — Frame evolution inside a single trigger
+% =========================================================
+t_sel = nTime; % pick last capture
+
+P_frame = squeeze(P(:,:,t_sel)); % [512 x nFrames]
+
+figure;
+surf(1:nFrames, f_axis, 10*log10(P_frame + 1e-12), 'EdgeColor','none');
+view(2);
+axis tight;
+
+xlabel('Frame Index');
+ylabel('Frequency (MHz)');
+title(['Channelizer Output Within DPW (Trigger ', num2str(t_sel), ')']);
+colorbar;

utilities/post_processing/checkTimeSamples.m

@@ -0,0 +1,84 @@
+%% =========================================================
+%  Data
+% =========================================================
+X = single(raw_DPW.Data);
+X = X(:,:,1:end); % first DPW useless (zeroed)
+
+%% =========================================================
+%  Parameters
+% =========================================================
+Fs = 512e6;        % Sampling rate (Hz)
+N  = 512;          % Frame size
+
+% Your data variable (rename if needed)
+% Expected size: [512 x 4 x 8]
+% X(frameSamples, frameIndex, timeIndex)
+% Example: X = your_workspace_variable;
+
+[nSamples, nFrames, nTime] = size(X);
+
+%% =========================================================
+%  FFT Computation
+% =========================================================
+FFT_all = zeros(N, nFrames*nTime);
+
+idx = 1;
+
+for t = 1:nTime
+    for f = 1:nFrames
+
+        x = X(:, f, t);
+
+        % Optional window (uncomment if needed)
+        % w = hann(N);
+        % x = x .* w;
+
+        Xf = fftshift(fft(x));
+        FFT_all(:, idx) = abs(Xf);
+
+        idx = idx + 1;
+    end
+end
+
+%% =========================================================
+%  Axes
+% =========================================================
+f_axis = (-N/2 : N/2-1) * (Fs/N) / 1e6; % MHz
+t_axis = 1:(nFrames*nTime);               % frame index
+
+%% =========================================================
+%  Spectrogram-like view (BEST)
+% =========================================================
+figure;
+surf(t_axis, f_axis, 20*log10(FFT_all + 1e-12), 'EdgeColor', 'none');
+view(2);
+axis tight;
+
+xlabel('Frame index');
+ylabel('Frequency (MHz)');
+title('FFT over time (per frame)');
+colorbar;
+
+%% =========================================================
+%  3D Visualization (optional)
+% =========================================================
+figure;
+surf(t_axis, f_axis, FFT_all, 'EdgeColor', 'none');
+xlabel('Frame index');
+ylabel('Frequency (MHz)');
+zlabel('Magnitude');
+title('3D FFT evolution');
+
+%% =========================================================
+%  Single frame debug (optional)
+% =========================================================
+figure;
+x_dbg = X(:,end,end);
+Xf_dbg = fftshift(fft(x_dbg));
+
+plot(f_axis, 20*log10(abs(Xf_dbg)+1e-12));
+grid on;
+
+xlabel('Frequency (MHz)');
+ylabel('Magnitude (dB)');
+title('Single Frame FFT');

utilities/soc_rfsoc_init.m

@@ -23,32 +23,44 @@ NCOCountIncDT = numerictype(1,NCOAccumWL*2,NCOAccumWL);
 
 %% Test signal parameters
 
-% Pulse width
-pulseWidth = 8.5e-6;
-
 % Pulse start/end frequencies
-pulseCentFreq = 125e6;
+pulseCentFreq = 0e6;
-pulseBw = 50e6; % Pulse bandwidth
+pulseBw = 40e6; % Pulse bandwidth
 
 % Number of pulses
-numPulses = 4;
+numPulses = 10;
 
 % Pulse repetition interval
-PRF = 20e3;
+PRF = 7.5e3;
 PRI = 1/PRF;
 
+
+% Pulse time duration
+%pulseT = 10; % use very long pulse help emulate CW
+pulseT = 20e-6;
+
+% CW mode (bypass pulse generation)
+%CwMode = false;
+
+% Counter mode (bypass pulse and CW generation)
+%CounterMode = true;
+
 % Output gain
 pulseGenGain = 1;
 
-%% Software parameters
+%% Simulation/External Mode parameters (conditional)
+bd = bdroot; % Retrive which model is calling this function
 
-% Signal generator update rate
+switch bd
-TsSW = 0.0025;
+    case 'soc_rfsoc_top'
-
+        TsSW = 0.0005; % Signal generator and capture update rate
-%% Simulation parameters
+        StopTime = 0.025; % Simulation total time
-
+    case 'gm_soc_rfsoc_top_sw'
-% Sim run time
+        TsSW = 0.25;
-stoptime = 10*TsSW;
+        StopTime = 250;
+    otherwise
+        error('rfsoc_init: InvalidModel (%s not supported).', bd);
+end
 
 %% Channelizer parameters
 
@@ -71,37 +83,8 @@ channelizerCoeffs = channelizer.coeffs.Numerator;
 %Starting frequency for each channel
 %chanFStart = chanBW/2:chanBW:(fs/2-chanBW/2);
 
-%Number of frames out of channelzier
+%Number of frames in the DPW
-nFrames = nChan/SamplesPerCycle;
+nFrames = 1024;%nChan/SamplesPerCycle;
 
 % Frame size after serializing x2
 %frameSize = SamplesPerCycle/2;
-
-
-
-
-
-% function soc_rfsoc_init(mdlPath)
-% % Initialization fcn for the model. It sets the model-wide params
-% % which are derived based on sample rate.
-% 
-% % 'FrameSize and 'NumBuffers' variables are set during model
-% % PreLoadFcn callback into base workspace. These two variables should be
-% % changed directly at the MATLAB command
-% 
-% % FrameSize = evalin('base','FrameSize');
-% 
-% dacSampleRate = get_param([mdlPath '/RF Data Converter'], 'dacSampleRate');
-% dacSampleRate = evalin('base', dacSampleRate)*1e6;
-% dacSamplesPerCycle = str2double(get_param([mdlPath '/RF Data Converter'], 'dacSamplesPerCycle'));
-% dacInterpolationMode = str2double(get_param([mdlPath '/RF Data Converter'], 'interpolationMode'));
-% streamClkFrequency = dacSampleRate/(dacSamplesPerCycle*dacInterpolationMode);
-% 
-% SampleTime = 1/streamClkFrequency;
-% 
-% % derived model-wide variables set into base workspace.
-% assignin('base','FPGAClkRate', streamClkFrequency);
-% assignin('base','TsFPGA', SampleTime);
-% assignin('base','SamplesPerCycle', dacSamplesPerCycle);
-% assignin('base','IntDecFactor', dacInterpolationMode);
-% end

utilities/soc_rfsoc_postload.m

@@ -1,5 +1,10 @@
+%% Check if top model is loaded
+if ~bdIsLoaded('soc_rfsoc_top')
+    load_system('soc_rfsoc_top');
+end
+
 %% Get parameters configured on the block 
-IntDecFactor = str2double(get_param([bdroot '/RF Data Converter'], ...
+IntDecFactor = str2double(get_param(['soc_rfsoc_top' '/RF Data Converter'], ...
     'interpolationMode')); % Interpolation and decimation factor
-SamplesPerCycle = str2double(get_param([bdroot '/RF Data Converter'], ...
+SamplesPerCycle = str2double(get_param(['soc_rfsoc_top' '/RF Data Converter'], ...
     'dacSamplesPerCycle')); % samples per FPGA cycle