1ebf8aa076
Updated Configuration Parameters (Code Generation -> Identifiers) in both soc_rfsoc_proc and parent model gm_soc_rfsoc_top_sw to set Maximum identifier length from 31 to 64. This avoids truncation of generated identifiers, reduces risk of name collisions, and ensures consistency across referenced models to prevent build mismatches.
📡 RFSoC Channelizer + PS Processing (R-ESM Prototype)
Overview
This project is based on the RFSoC SoC Blockset reference design, adapted as a prototype for a Radar Electronic Support Measures (R-ESM) receiver.
The system implements a high-throughput signal chain in the FPGA (PL) and performs frame-based processing in the processor (PS).
Current Status
- Tx subsystem: LFM pulse generator (DDS-based, complex output)
- Rx subsystem: fully functional channelizer pipeline (PFB-based)
- PL → PS interface: AXI4-Stream + DMA operational
- PS processing: frame-based algorithm (RMS + peak detection)
System Architecture
ADC → Channelizer (PFB, 512 bins)
→ FFT_Capture (frame control)
→ FIFO Serializer (4 FIFOs → 1 stream)
→ AXI4-Stream (uint64)
→ DMA (S2MM)
→ PS Memory
→ Processor Algorithm
Key Parameters
- ADC Sampling Rate: 4096 MSPS
- Decimation: 8
- Effective BW: 512 MHz
- Channels (FFT size): 512
- Samples per clock: 4
- FPGA clock: 128 MHz
- Frame size (PS): 512 samples
📚 Documentation
FPGA (PL)
Processor (PS)
System Flow
Tx → Rx → PS
- Tx generates waveform
- Rx captures and channelizes
- PS processes frames
Roadmap
- Functional FrFT (PS)
- Profiling
- NEON optimization
- Throughput tuning
- PL acceleration
Key Takeaway
First make it work end-to-end, then make it fast.