3.0 KiB
3.0 KiB
📡 PL Rx Subsystem (Channelizer)
Overview
The Rx subsystem implements a polyphase filter bank (PFB) channelizer followed by FFT processing.
It converts wideband ADC input into frequency-domain channels and streams the result to the PS.
A bypass path is also available for raw data inspection and debugging.
Architecture
Channelizer Path (default)
ADC ↓ PFB Channelizer (Decimation + Filtering) ↓ FFT (512 bins) ↓ FFT Capture ↓ FIFO Serializer (4 → 1) ↓ AXI4-Stream ↓ DMA
Bypass Path (Debug / Raw Data)
ADC ↓ Bypass Path ↓ FIFO / Serializer ↓ AXI4-Stream ↓ DMA
Bypass Functionality
The bypass allows direct observation of the input signal without channelization.
Purpose
- Debugging and validation
- Access to raw ADC-domain data
- Comparison with channelized output
- Verification of downstream processing
Behavior
- Input data is routed directly to output
- No filtering or FFT applied
- Maintains same output interface (AXI4-Stream)
Selection Mechanism
A selector signal chooses between:
- Channelizer output (normal operation)
- Bypass output (raw data)
Implementation typically uses:
- Parallel paths
- Output switching logic
Processing Chain (Channelizer Mode)
ADC Input
- Sampling rate: 4096 MSPS
- Data type: fixdt(1,16,15) (Q1.15 format)
PFB Channelizer
- Decimation: 8
- Effective bandwidth: 512 MHz
- Input and internal scaling aligned to Q1.15 domain
FFT
- Size: 512
- Produces frequency bins
FFT Capture
- Controls frame boundaries
FIFO Serializer
- Converts parallel streams into single stream
Numeric Format and Scaling
System Standardization
The signal chain was standardized to a Q1.15 fixed-point format (fixdt(1,16,15)):
- DAC output uses Q1.15
- ADC input is reinterpreted as Q1.15 (Same Stored Integer)
- Channelizer input operates in this normalized domain
Channelizer Output Scaling
- Native channelizer output: sFix25_En23
- Rescaled and quantized to: fixdt(1,16,15)
This conversion:
- Preserves signal dynamic range
- Maximizes fractional precision
- Uses rounding and saturation
- Aligns with system-wide numeric format
Data Width Reduction
- Previous format: 50 bits per complex sample (25 bits real + 25 bits imag)
- New format: 32 bits per complex sample (16 bits real + 16 bits imag)
Benefits:
- Reduced AXI bandwidth
- Reduced FIFO usage
- More efficient DMA transfers
AXI4-Stream Output
- Data type: uint32 (packed complex: 16-bit real + 16-bit imag)
- TLAST = frame boundary
Data Format
- Frame size: 512 samples
- Complex samples packed into 32-bit words
Key Characteristics
- Fully streaming pipeline
- High throughput
- Deterministic latency
- Consistent fixed-point scaling (Q1.15 end-to-end)
- Supports dual-mode operation (channelizer / bypass)