canisio
286c464f5a
set SoCData as datatype again on the stream read inport (I dont know if this was the problem, but its working again)
2026-04-20 15:04:14 -03:00
canisio
91b02cdc79
organized register... stopped working
2026-04-20 11:53:26 -03:00
canisio
d8fe924f6e
tests before trying in the board
2026-04-20 10:49:21 -03:00
canisio
b2ce956f41
Multi-frame capture integrated into full design with trigger-controlled DPW; AXI stream (uint32 [4x1]) and DMA framing aligned; fixed FSM termination condition (no overflow); validated end-to-end (PL→DMA→PS) using counter input for multiple nFrames
2026-04-17 17:03:34 -03:00
canisio
fc50e71ab5
AXI stream updated to uint32 [4x1] format; samples-per-frame aligned to nFrames×512; PS stream read configured accordingly; single-frame (nFrames=1) validated end-to-end (PL→DMA→PS) with correct unpacking and data integrity
2026-04-17 12:22:12 -03:00
canisio
ce87190fba
If sw side of AXI4-Stream to Software block is set to fixdt(128), frames appear to be arriving correctly on PS. However, reinterpretation is failing when using option "uint32"
2026-04-17 11:33:18 -03:00
canisio
15f20619b1
MultiFrame camputre PL part integrated (no test, no PS)
2026-04-16 17:25:28 -03:00
canisio
5e5bba3ce6
Stable 16-bit Q1.15 Rx chain before AXI width upgrade
2026-04-14 09:25:01 -03:00
canisio
ccc6b9cd73
Validate 16-bit Q1.15 Rx chain (baseline, partial validation)
...
Standardized ADC/DAC and channelizer input to fixdt(1,16,15)
Rescaled channelizer output from sFix25_En23 to 16-bit complex
Verified channelizer path and spectrum behavior in full simulation
Bypass path and datatype tuning (coefficients/output) pending validation
2026-04-13 17:47:08 -03:00
canisio
d4e53a67ee
Stable single frame (512 samples) baseline before capture redesign
2026-04-09 09:27:44 -03:00
canisio
2e570cee8b
Created folder and test bench model for new capture block. Copied from current version.
2026-04-08 15:50:59 -03:00
canisio
520a37f520
CW mode integrated to design
2026-04-08 15:00:47 -03:00
canisio
cd91e3066b
added CW mode (with LFM) to the chirp block (TB, not integrated yet)
2026-04-08 12:19:03 -03:00
canisio
5a3bc8891d
cleaned up log signals (still not working)
2026-04-07 09:26:50 -03:00
canisio
84b795203a
pulse generator integrated but not working
2026-04-06 16:16:42 -03:00
canisio
ada7e324cd
Fixed register address on "update parameters"
2026-04-06 15:15:55 -03:00
canisio
05b74503dc
Fixed init callback for pulse gen testbench
2026-04-06 10:45:21 -03:00
canisio
3c6ae0cfe9
finished organization of init funcions and parameters
2026-04-04 16:05:17 -03:00
canisio
eb14676581
Oganize preload and init functions and parameters (ongoing)
2026-04-04 15:16:58 -03:00
canisio
f66c3ffd06
Changed interface model to reflect bypass
2026-03-31 17:51:26 -03:00
canisio
66ad6149e6
Added switch and led (physical)
2026-03-31 16:41:27 -03:00
canisio
a9b4ad9e17
Added bypass toggle via memory mapped register
2026-03-31 16:17:34 -03:00
canisio
0ea6881d1e
Added bypass to Rx on FPGA. Test OK
2026-03-31 15:55:46 -03:00
canisio
10644b0475
added README
2026-03-27 18:41:29 -03:00
canisio
89ecf79e61
Added comment os PS system. Info from training says the time-driven tasks are all inside the processor block, except the event driven and the initialize
2026-03-27 17:17:28 -03:00
canisio
13263f4f33
Removed one of the channels and respective beamforming on Tx and Rx. Simulation ok. Kept the read registers of the angles as placeholders for future use.
2026-03-27 16:51:41 -03:00
canisio
584db6233c
- Added utilities for frequency planning
...
- Changed freq plane to: Fs 4096, int/dec 8X, Mixers 768
2026-03-27 12:50:10 -03:00
canisio
d5bbdfb435
Changed NCO on AD/DA to 0Hz. Changed language for HDL IP to Verilog. Cleaned up for new soc_prj generation
2026-03-25 18:23:42 -03:00
canisio
c86497656b
Changed fs to 1024MSPS and added double-sided spectrum visualization. FFT Shifit with two selectors and one concatenate
2026-03-24 18:10:26 -03:00
canisio
ac2e7bcece
Initial
2026-03-24 12:44:45 -03:00
