canisio
edef1dbed3
validation: add checkCounterSamples and verify capture up to 1024 frames on ZCU111
...
Created checkCounterSamples.m to validate sample continuity, counter wraps,
and frame index progression. Verified counter bypass, sine bypass, and
channelizer modes up to nFrames=1024 across 10 DPWs on ZCU111.
2026-04-27 18:32:31 -03:00
canisio
f9a2eff397
validate sine over bypass using a post processing script in the logged data. Added folter post_processing and script checkTimeSamples
2026-04-25 11:28:43 -03:00
canisio
cb56e78923
changed folder name for all testbench models
2026-04-17 08:31:14 -03:00
canisio
beb5410390
added visualisation to validate ouput of multiple frames
2026-04-16 11:56:25 -03:00
canisio
2e570cee8b
Created folder and test bench model for new capture block. Copied from current version.
2026-04-08 15:50:59 -03:00
canisio
3c6ae0cfe9
finished organization of init funcions and parameters
2026-04-04 16:05:17 -03:00
canisio
eb14676581
Oganize preload and init functions and parameters (ongoing)
2026-04-04 15:16:58 -03:00
canisio
040834d511
added docs folder to project path.
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tested remotely. OK
2026-04-03 20:47:13 -03:00
canisio
ea0ecefae1
Added documentation and updated README
2026-04-02 17:29:24 -03:00
canisio
e810145620
Pulse Generator TB validated
2026-04-02 17:08:44 -03:00
canisio
8e397fa41e
Added draft to TBm_chirp model. Added init function script to testbench
2026-04-02 12:03:59 -03:00
canisio
790c2fdb37
added placeholder for chirp block
2026-04-01 12:05:57 -03:00
canisio
f66c3ffd06
Changed interface model to reflect bypass
2026-03-31 17:51:26 -03:00
canisio
278e318715
Added simulink model to testbench bypass funcion (bypass folder)
2026-03-31 14:26:45 -03:00
canisio
e0765a6afe
Added bypass funcion and its testbench (bypass folder)
2026-03-31 14:25:43 -03:00
canisio
dd70d58f2a
Added frtt_codegen folder to the project initialization
2026-03-31 09:19:28 -03:00
canisio
d8a9e026ff
Added testbench for simulink model. Added f0 option to both testbenches
2026-03-30 16:01:46 -03:00
canisio
1613ae8ad9
Ran codegen for mex and tested. Working ok
2026-03-30 11:44:31 -03:00
canisio
7b04d52204
Added frft functions towards codegen (c code on PS)
2026-03-30 11:16:12 -03:00
canisio
10644b0475
added README
2026-03-27 18:41:29 -03:00
canisio
43f91b281b
Tested on board. Running ok. Updated interface model and added shortcut to it.
2026-03-27 17:52:13 -03:00
canisio
584db6233c
- Added utilities for frequency planning
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- Changed freq plane to: Fs 4096, int/dec 8X, Mixers 768
2026-03-27 12:50:10 -03:00
canisio
d5bbdfb435
Changed NCO on AD/DA to 0Hz. Changed language for HDL IP to Verilog. Cleaned up for new soc_prj generation
2026-03-25 18:23:42 -03:00
canisio
89c8003f5a
Added sw interface model (controls hardware running on board).
2026-03-25 17:21:09 -03:00
canisio
7c1292ae5c
Added startup function to project (setup HDL tool on it)
2026-03-25 16:15:16 -03:00
canisio
ac2e7bcece
Initial
2026-03-24 12:44:45 -03:00
