update diagram (added Simulink)

Formatted top diagrams

.gitignore

@@ -49,3 +49,15 @@ soc_rfsoc_top_sw_ert_rtw/
 # SimBiology backup files
 *.sbproj.backup
 *.sbproj.bak
+
+/codegen_fracFdpw/fracF_dpw0_ert_rtw/
+
+/codegen_fracFdpw/fracF_dpw0
+
+/codegen_fracFdpw/FrFT_ert_rtw/
+
+/codegen_fracFdpw/TBm_fracFdpw_ert_rtw/
+
+/codegen_fracFdpw/FrFT
+
+*.lock

README.md

@@ -11,22 +11,37 @@ The system implements a high-throughput signal chain in the FPGA (PL) and perfor
 ## Current Status
 
 - Tx subsystem: LFM pulse generator (DDS-based, complex output)
-- Rx subsystem: fully functional channelizer pipeline (PFB-based)
+- Rx subsystem: fully functional channelizer pipeline (PFB-based) or bypass
 - PL → PS interface: AXI4-Stream + DMA operational
-- PS processing: frame-based algorithm (RMS + peak detection)
+- PS processing: frame-based algorithm on a Data Process Window (DPW)
 
 ---
 
 ## System Architecture
 
-ADC → Channelizer (PFB, 512 bins)  
-→ FFT_Capture (frame control)  
-→ FIFO Serializer (4 FIFOs → 1 stream)  
-→ AXI4-Stream (uint64)  
+Tx (PL)  
+→ Waveform Generator (LFM / CW / Pulsed)  
+→ DAC  
+→ RF Loopback / Input  
+
+Rx (PL)   
+→ ADC  
+→ Channelizer (PFB, 512 bins) / Bypass / Counter  
+→ Capture (frame control)  
+→ AXI4-Stream (128-bit, 4 samples/clock)  
 → DMA (S2MM)  
 → PS Memory  
 → Processor Algorithm
 
+Post Processing (PS)  
+→ Triggered Capture  
+→ Sample Unpacking (I/Q)  
+→ Data Reshaping → [FrameSize x nFrames x nTriggers]  
+→ Host Communication / Processing / Visualization
+→ One DPW is a windows of FrameSize x nFrames samples
+
+![High-level system architecture](./docs/img/resm_diagram.svg)
+
 ---
 
 ## Key Parameters

codegen_fracFdpw/TBc_fracFdpwLFM.m

@@ -0,0 +1,279 @@
+%% Test fracF_dpw using a physical LFM
+%
+% Parameters chosen to match previous FrFT validation work:
+%
+%   Fs   = 512 MHz
+%   T    = 1 us
+%   B    = 64 MHz
+%
+% Matched FrFT order:
+%
+%   a = -(2/pi)*atan(Fs/(beta*T))
+%
+% where:
+%
+%   beta = B/T
+%
+% Notes:
+%   - FFT is computed on the original (non-interpolated) signal.
+%   - FrFT is computed on the interpolated signal.
+%   - Power spectra are averaged across the entire DPW.
+
+clearvars -except out
+clc
+close all
+
+%% Signal parameters
+
+N       = 512;
+Nframes = 1024;
+
+Fs = single(512e6);
+T  = single(1e-6);
+
+B    = single(32e6);
+beta = B/T;
+
+%% Time axis
+
+t = single((-N/2:N/2-1).') / Fs;
+
+%% Generate LFM
+
+x = exp(1j*pi*beta*(t.^2));
+
+x = complex(single(real(x)), ...
+            single(imag(x)));
+
+%% Create DPW
+
+X = repmat(x,1,Nframes);
+
+%% Interpolate exactly as Simulink
+
+halfbandInterp = dsp.FIRHalfbandInterpolator;
+
+Xint = halfbandInterp(X);
+
+%% Matched FrFT order
+
+aMatch = single(-(2/pi)*atan(Fs/(beta*T)));
+
+fprintf('\n');
+fprintf('Fs      = %.3f MHz\n',double(Fs)/1e6);
+fprintf('T       = %.3f us\n',double(T)*1e6);
+fprintf('B       = %.3f MHz\n',double(B)/1e6);
+fprintf('aMatch  = %.6f\n',double(aMatch));
+
+%% FFT reference
+%
+% FFT detector operates on the original non-interpolated signal.
+
+FFTref = fftshift(fft(X,[],1),1)/N;
+
+%% FrFT
+%
+% FrFT detector operates on the interpolated signal.
+
+[Achirp,H,Cchirp,Aa] = fracF_init(aMatch);
+
+Ffrft = fracF_dpw( ...
+    Xint,...
+    Achirp,...
+    H,...
+    Cchirp,...
+    Aa);
+
+%% Mean power spectrum across the DPW
+
+Pfft = mean(abs(FFTref).^2,2);
+
+Pfrft = mean(abs(Ffrft).^2,2);
+
+%% Peak comparison
+
+peakFFT  = max(Pfft);
+peakFrFT = max(Pfrft);
+
+gain_dB = 10*log10(double(peakFrFT/peakFFT));
+
+fprintf('\n');
+fprintf('FFT peak power       : %.6f\n',double(peakFFT));
+fprintf('FrFT peak power      : %.6f\n',double(peakFrFT));
+fprintf('Processing gain      : %.3f dB\n',gain_dB);
+
+%% Normalize spectra for display
+
+Pfft_dB = 10*log10(Pfft/max(Pfft));
+
+Pfrft_dB = 10*log10(Pfrft/max(Pfrft));
+
+%% Display averaged spectra
+
+figure
+
+subplot(2,1,1)
+
+plot(Pfft_dB)
+
+grid on
+
+ylim([-60 5])
+
+title('FFT Mean Power Spectrum')
+xlabel('FFT Bin')
+ylabel('Power (dB)')
+
+subplot(2,1,2)
+
+plot(Pfrft_dB)
+
+grid on
+
+ylim([-60 5])
+
+title(sprintf('FrFT Mean Power Spectrum (a = %.6f)', ...
+      double(aMatch)))
+
+xlabel('FrFT Bin')
+ylabel('Power (dB)')
+
+%% Report peak locations
+
+[~,idxFFT]  = max(Pfft);
+[~,idxFrFT] = max(Pfrft);
+
+fprintf('\n');
+fprintf('FFT peak bin        : %d\n',idxFFT);
+fprintf('FrFT peak bin       : %d\n',idxFrFT);
+fprintf('\n');
+
+%% Compare TBc against TBm (optional)
+%
+% If the Simulink model has been executed and produced out.Fsim,
+% compare both implementations.
+
+if exist('out','var')
+
+    fprintf('\n');
+    fprintf('TBc vs TBm Comparison\n');
+    fprintf('---------------------\n');
+
+    Ftbm = out.Fsim;
+
+    %% Dimension check
+
+    fprintf('TBc size : [%d %d]\n', ...
+            size(Ffrft,1), size(Ffrft,2));
+
+    fprintf('TBm size : [%d %d]\n', ...
+            size(Ftbm,1), size(Ftbm,2));
+
+    assert(isequal(size(Ffrft),size(Ftbm)), ...
+           'TBc and TBm dimensions differ.');
+
+    %% Error metrics
+
+    err = Ftbm - Ffrft;
+
+    maxErr = max(abs(err(:)));
+
+    rmsErr = sqrt(mean(abs(err(:)).^2));
+
+    refPeak = max(abs(Ffrft(:)));
+
+    relErr = maxErr / refPeak;
+
+    %% Results
+
+    fprintf('\n');
+    fprintf('Reference peak    : %.9g\n',double(refPeak));
+    fprintf('Maximum error     : %.9g\n',double(maxErr));
+    fprintf('RMS error         : %.9g\n',double(rmsErr));
+    fprintf('Relative error    : %.9g\n',double(relErr));
+
+    if maxErr == 0
+
+        fprintf('\nPASS: Outputs are bit-identical.\n');
+
+    elseif relErr < 1e-5
+
+        fprintf('\nPASS: Outputs are numerically equivalent.\n');
+
+    else
+
+        fprintf('\nWARNING: Outputs differ.\n');
+
+    end
+
+    %% Visual comparison
+
+    frameIdx = 1;
+
+    figure
+
+    subplot(3,1,1)
+
+    plot(abs(Ffrft(:,frameIdx)))
+
+    grid on
+
+    title('TBc Output')
+    xlabel('Bin')
+    ylabel('|F|')
+
+    subplot(3,1,2)
+
+    plot(abs(Ftbm(:,frameIdx)))
+
+    grid on
+
+    title('TBm Output')
+    xlabel('Bin')
+    ylabel('|F|')
+
+    subplot(3,1,3)
+
+    plot(abs(Ftbm(:,frameIdx) - Ffrft(:,frameIdx)))
+
+    grid on
+
+    title('Absolute Error')
+    xlabel('Bin')
+    ylabel('|Error|')
+
+    %% Mean power spectrum comparison
+
+    Ptbc = mean(abs(Ffrft).^2,2);
+
+    Ptbm = mean(abs(Ftbm).^2,2);
+
+    Ptbc_dB = 10*log10(Ptbc/max(Ptbc));
+
+    Ptbm_dB = 10*log10(Ptbm/max(Ptbm));
+
+    figure
+
+    plot(Ptbc_dB,'LineWidth',1.5)
+
+    hold on
+
+    plot(Ptbm_dB,'--','LineWidth',1.5)
+
+    grid on
+
+    ylim([-60 5])
+
+    xlabel('Bin')
+    ylabel('Power (dB)')
+
+    title('TBc vs TBm Mean Power Spectrum')
+
+    legend('TBc','TBm')
+
+else
+
+    fprintf('\n');
+    fprintf('TBm comparison skipped (out.Fsim not found).\n');
+
+end

codegen_fracFdpw/TBc_fracFdpwNO.m

@@ -0,0 +1,69 @@
+%% fracF_dpw verification
+%
+% Verifies numerical equivalence between:
+%   - fracF_cg()  : single-frame implementation
+%   - fracF_dpw() : DPW-aware implementation
+%
+% The test processes a full DPW of random complex data and compares the
+% outputs sample-by-sample.
+
+clear
+clc
+
+%% Test parameters
+
+a = single(1);
+
+N       = 1024;
+Nframes = 1024;
+
+%% Precompute FrFT coefficients
+
+[Achirp,H,Cchirp,Aa] = fracF_init(a);
+
+%% Generate random complex DPW
+
+X = complex( ...
+    randn(N,Nframes,'single'), ...
+    randn(N,Nframes,'single'));
+
+%% DPW implementation
+
+Fdpw = fracF_dpw( ...
+    X,...
+    Achirp,...
+    H,...
+    Cchirp,...
+    Aa);
+
+%% Reference implementation
+
+Fref = complex(zeros(512,Nframes,'single'));
+
+for k = 1:Nframes
+    Fref(:,k) = fracF_cg(X(:,k),a);
+end
+
+%% Error metrics
+
+err = Fdpw - Fref;
+
+maxErr = max(abs(err(:)));
+rmsErr = sqrt(mean(abs(err(:)).^2));
+
+%% Results
+
+fprintf('\n');
+fprintf('FrFT DPW Verification\n');
+fprintf('---------------------\n');
+fprintf('Order (a)      : %.6f\n',a);
+fprintf('Frame size     : %d\n',N);
+fprintf('Number frames  : %d\n',Nframes);
+fprintf('Max error      : %.9g\n',double(maxErr));
+fprintf('RMS error      : %.9g\n',double(rmsErr));
+
+if maxErr == 0
+    fprintf('\nPASS: Outputs are bit-identical.\n');
+else
+    fprintf('\nPASS: Outputs are numerically equivalent.\n');
+end

codegen_fracFdpw/fracF_dpw.m

@@ -0,0 +1,116 @@
+function F = fracF_dpw(f,...
+                       Achirp,...
+                       H,...
+                       Cchirp,...
+                       Aa)
+%#codegen
+%% fracF_dpw  Fractional Fourier Transform for an entire DPW
+%
+%   F = fracF_dpw(f,Achirp,H,Cchirp,Aa)
+%
+%   Computes the Fractional Fourier Transform (FrFT) of all frames in a
+%   Digital Processing Window (DPW) using a matrix-oriented implementation.
+%
+%   The algorithm follows the same chirp-convolution-chirp formulation as
+%   fracF_cg(), but processes all DPW frames simultaneously. Each column of
+%   the input matrix is treated as an independent frame, following the same
+%   "columns are channels" convention used by DSP System Toolbox blocks.
+%
+%   Processing chain:
+%
+%       f
+%        ↓
+%     Achirp
+%        ↓
+%     Zero-pad
+%        ↓
+%        FFT
+%        ↓
+%         H
+%        ↓
+%       IFFT
+%        ↓
+%     Extract
+%        ↓
+%     Cchirp
+%        ↓
+%        Aa
+%        ↓
+%         F
+%
+%   INPUTS
+%       f        [1024 x Nframes] complex(single)
+%                Interpolated DPW. Each column corresponds to one frame.
+%
+%       Achirp   [1024 x 1] complex(single)
+%                Pre-multiplication chirp (A chirp).
+%
+%       H        [2048 x 1] complex(single)
+%                FFT of the convolution chirp (B chirp).
+%
+%       Cchirp   [512 x 1] complex(single)
+%                Post-multiplication chirp (C chirp).
+%
+%       Aa       scalar complex(single)
+%                FrFT amplitude factor (A_alpha).
+%
+%   OUTPUT
+%       F        [512 x Nframes] complex(single)
+%                FrFT result for all DPW frames.
+%
+%   Notes
+%       - Input length is fixed at N = 1024 samples.
+%       - Output length is N/2 = 512 samples.
+%       - All DPW frames are processed simultaneously.
+%       - Numerically equivalent to applying fracF_cg() independently to
+%         each column of the input matrix.
+%       - Intended for code generation and RFSoC PS deployment.
+%
+%   See also:
+%       fracF_init
+%       fracF_cg
+
+%% Fixed transform dimensions
+
+N    = 1024;
+Nfft = 2048;
+
+%% DPW dimensions
+
+Nframes = size(f,2);
+
+%% Pre-multiplication chirp (A chirp)
+
+g = f .* Achirp;
+
+%% Zero-padding
+%
+% Extend each frame from N to Nfft samples to perform the linear
+% convolution through frequency-domain multiplication.
+
+g_pad = complex(zeros(Nfft,Nframes,'single'));
+
+g_pad(1:N,:) = g;
+
+%% Frequency-domain convolution
+%
+% Compute the convolution with the B chirp using the FFT method.
+
+Gfft = fft(g_pad);
+
+G = ifft(Gfft .* H);
+
+%% Extract valid convolution region and decimate
+%
+% The Ozaktas formulation requires only the valid portion of the
+% convolution result, followed by a factor-of-two decimation.
+
+G_valid = G(N+1:2:end,:);
+
+%% Post-multiplication chirp (C chirp)
+%
+% Apply the final chirp and amplitude factor to obtain the FrFT output.
+
+F = Aa .* G_valid .* Cchirp;
+
+end

codegen_fracFdpw/fracF_init.m

@@ -0,0 +1,115 @@
+function [Achirp,H,Cchirp,Aa] = fracF_init(a)
+%#codegen
+%% fracF_init  Precompute FrFT coefficients
+%
+%   [Achirp,H,Cchirp,Aa] = fracF_init(a)
+%
+%   Generates the constant coefficients required by the code-generation
+%   implementation of the Fractional Fourier Transform (FrFT).
+%
+%   The implementation follows the chirp-convolution-chirp formulation:
+%
+%       f(n)
+%         ↓
+%      Achirp
+%         ↓
+%        FFT
+%         ↓
+%      H = FFT(Bchirp)
+%         ↓
+%       IFFT
+%         ↓
+%      Cchirp
+%         ↓
+%         Aa
+%         ↓
+%       F_a(n)
+%
+%   These coefficients depend only on the transform order 'a' and can
+%   therefore be computed once and reused for all frames within a DPW.
+%
+%   INPUT
+%       a       FrFT order (single)
+%
+%   OUTPUTS
+%       Achirp  [1024 x 1] pre-multiplication chirp (A chirp)
+%       H       [2048 x 1] FFT of the convolution chirp (B chirp)
+%       Cchirp  [512  x 1] post-multiplication chirp (C chirp)
+%       Aa      scalar FrFT amplitude factor (A_alpha)
+%
+%   Notes
+%       - Input length is assumed to be N = 1024 samples.
+%       - Output length is N/2 = 512 samples.
+%       - All outputs are returned as complex(single).
+%       - Intended for use with fracF_dpw().
+%
+%   See also:
+%       fracF_dpw
+
+%% Fixed transform dimensions
+
+N = 1024;
+
+%% Transform parameters
+
+pi_s = single(pi);
+
+phi = a * (pi_s/2);
+
+tan_half_phi = tan(phi/2);
+sin_phi      = sin(phi);
+cos_phi      = cos(phi);
+
+csc_phi = 1/sin_phi;
+cot_phi = cos_phi/sin_phi;
+
+two_delta = 2*sqrt(single(N)/2);
+
+%% Pre-multiplication chirp (A chirp)
+
+n = single((-N/2:N/2-1).') / two_delta;
+
+Achirp = exp(-1j*pi_s*(n.^2)*tan_half_phi);
+
+%% Convolution chirp (B chirp)
+
+m = single((-N:N-1).') / two_delta;
+
+Bchirp = exp(1j*pi_s*csc_phi*(m.^2));
+
+%% Frequency-domain convolution kernel
+%
+% H corresponds to FFT(Bchirp) and is used in the frequency-domain
+% implementation of the chirp convolution.
+
+H = fft(Bchirp);
+
+%% Post-multiplication chirp (C chirp)
+%
+% Since the implementation extracts every other sample from the valid
+% convolution region, only the corresponding chirp samples are required.
+
+Cchirp = Achirp(1:2:end);
+
+%% FrFT amplitude factor (A_alpha)
+
+Aa = sqrt(1 - 1j*cot_phi) / two_delta;
+
+%% Force complex(single) outputs
+%
+% Explicit casting avoids unintended promotion to double precision and
+% ensures deterministic code generation.
+
+Achirp = complex(single(real(Achirp)), ...
+                 single(imag(Achirp)));
+
+H = complex(single(real(H)), ...
+            single(imag(H)));
+
+Cchirp = complex(single(real(Cchirp)), ...
+                 single(imag(Cchirp)));
+
+Aa = complex(single(real(Aa)), ...
+             single(imag(Aa)));
+
+end

codegen_frft/TBc_lfm_fracF.m

@@ -1,4 +1,4 @@
-%% FrFT Validation Script (Reference vs Original)
+  %% FrFT Validation Script (Reference vs Original)
 % Author: Canisio Barth
 
 clear; clc; close all;

docs/img/resm_diagram.drawio

@@ -0,0 +1,236 @@
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docs/pl_rx_subsystem.md

@@ -6,11 +6,9 @@
 
 ## Overview
 
-The Rx subsystem implements a **polyphase filter bank (PFB) channelizer** followed by FFT processing.
+The Rx subsystem implements a **polyphase filter bank (PFB) channelizer** followed by FFT processing, a **bypass path**, and a **multi-frame capture pipeline**.
 
-It converts wideband ADC input into frequency-domain channels and streams the result to the PS.
-
-A **bypass path** is also available for raw data inspection and debugging.
+It converts wideband ADC input into frequency-domain channels (or raw samples via bypass) and streams the result to the PS.
 
 ---
 
@@ -24,11 +22,9 @@ PFB Channelizer (Decimation + Filtering)
  ↓  
 FFT (512 bins)  
  ↓  
-FFT Capture
+Capture (frame control)  
  ↓  
-FIFO Serializer (4 → 1)
- ↓
-AXI4-Stream
+AXI4-Stream (128-bit, 4 samples/clock)  
  ↓  
 DMA
 
@@ -40,45 +36,26 @@ ADC
  ↓  
 Bypass Path  
  ↓  
-FIFO / Serializer
+Capture (frame control)  
  ↓  
-AXI4-Stream
+AXI4-Stream (128-bit, 4 samples/clock)  
  ↓  
 DMA
 
 ---
 
-## Bypass Functionality
+## Capture Pipeline
 
-The bypass allows direct observation of the input signal without channelization.
-
-### Purpose
-
-- Debugging and validation
-- Access to raw ADC-domain data
-- Comparison with channelized output
-- Verification of downstream processing
-
----
+- Multi-frame acquisition (configurable nFrames)
+- Frame size: 512 samples
+- Supports asynchronous capture start (not frame-aligned)
+- TLAST asserted at frame boundaries
 
 ### Behavior
 
-- Input data is routed directly to output
-- No filtering or FFT applied
-- Maintains same output interface (AXI4-Stream)
-
----
-
-### Selection Mechanism
-
-A selector signal chooses between:
-
-- Channelizer output (normal operation)
-- Bypass output (raw data)
-
-Implementation typically uses:
-- Parallel paths
-- Output switching logic
+- First frame may be partial
+- Frames may contain ≤ 2 frame indices (expected)
+- DPW spans nFrames frames but covers nFrames + 1 frame regions
 
 ---
 
@@ -86,22 +63,19 @@ Implementation typically uses:
 
 ### ADC Input
 - Sampling rate: 4096 MSPS
-- Data type: **fixdt(1,16,15)** (Q1.15 format)
+- Data type: **fixdt(1,16,15)** (Q1.15)
 
 ### PFB Channelizer
 - Decimation: 8
 - Effective bandwidth: 512 MHz
-- Input and internal scaling aligned to Q1.15 domain
 
 ### FFT
 - Size: 512
 - Produces frequency bins
 
-### FFT Capture
-- Controls frame boundaries
-
-### FIFO Serializer
-- Converts parallel streams into single stream
+### Capture
+- Defines frame boundaries (512 samples)
+- Generates TLAST
 
 ---
 
@@ -109,62 +83,57 @@ Implementation typically uses:
 
 ### System Standardization
 
-The signal chain was standardized to a **Q1.15 fixed-point format (fixdt(1,16,15))**:
-
-- DAC output uses Q1.15
-- ADC input is reinterpreted as Q1.15 (Same Stored Integer)
-- Channelizer input operates in this normalized domain
-
----
+- End-to-end Q1.15 (**fixdt(1,16,15)**)
 
 ### Channelizer Output Scaling
 
-- Native channelizer output: **sFix25_En23**
-- Rescaled and quantized to: **fixdt(1,16,15)**
-
-This conversion:
-
-- Preserves signal dynamic range
-- Maximizes fractional precision
-- Uses rounding and saturation
-- Aligns with system-wide numeric format
+- Native: **sFix25_En23**
+- Quantized to: **fixdt(1,16,15)** (round + saturate)
 
 ---
 
-### Data Width Reduction
+## Data Packing (Updated)
 
-- Previous format: **50 bits per complex sample** (25 bits real + 25 bits imag)
-- New format: **32 bits per complex sample** (16 bits real + 16 bits imag)
+- 4 samples per clock
+- Each sample: complex (16-bit real + 16-bit imag)
+- Packed into **128-bit AXI4-Stream word**
 
 Benefits:
-
-- Reduced AXI bandwidth
-- Reduced FIFO usage
-- More efficient DMA transfers
+- Matches datapath parallelism
+- Efficient DMA transfers
+- Eliminates need for serializer stage
 
 ---
 
 ## AXI4-Stream Output
 
-- Data type: uint32 (packed complex: 16-bit real + 16-bit imag)
+- Width: 128 bits
+- Contains 4 complex samples per cycle
 - TLAST = frame boundary
 
 ---
 
-## Data Format
+## Debug / Validation Features
 
-- Frame size: 512 samples
-- Complex samples packed into 32-bit words
+A counter-based debug mode is implemented:
+
+- Real part → sample counter (0..511)
+- Imag part → frame index
+
+Used to validate:
+- Sample continuity
+- Frame boundaries
+- DMA ordering and integrity
 
 ---
 
 ## Key Characteristics
 
 - Fully streaming pipeline
-- High throughput
 - Deterministic latency
-- Consistent fixed-point scaling (Q1.15 end-to-end)
-- Supports dual-mode operation (channelizer / bypass)
+- High throughput (4 samples/clock)
+- Dual-mode operation (channelizer / bypass)
+- Validated up to nFrames = 1024
 
 ---
 

docs/ps_subsystem.md

@@ -1,4 +1,4 @@
-# 🧠 PS Subsystem (Control + Processing)
+# 🧠 PS Subsystem (Control + Capture + Processing)
 
 [🏠 Project Home](../README.md)
 
@@ -8,78 +8,287 @@
 
 The PS subsystem is responsible for:
 
-- Configuring PL subsystems
-- Receiving data via DMA
-- Performing frame-based processing
+* System initialization
+* Configuring PL subsystems
+* Triggering captures
+* Receiving data via DMA
+* Preparing data for processing and visualization
+
+The subsystem now includes an initial **FrFT-based processing chain** implemented in Simulink and targeted to the RFSoC Processing System (PS).
+
+Current work focuses on:
+
+* Algorithm validation
+* Code generation
+* Hardware integration
+* Performance characterization
+
+while maintaining reliable data acquisition and host interaction.
 
 ---
 
 ## Responsibilities
 
-### Control
+### Control & Initialization
 
-- Writes parameters to PL registers:
-  - Tx generator configuration
-- Generates TxPulseStart trigger
+* Configure PL parameters:
+
+  * Tx waveform configuration
+  * Capture parameters (nFrames, etc.)
+* Initialize DMA and memory buffers
+* Manage system startup
+
+---
+
+### Trigger & Capture
+
+* Generates capture trigger (software-controlled)
+* Controls DPW acquisition timing
+* Each trigger initiates one DPW capture
 
 ---
 
 ### DMA Handling
 
-- AXI4-Stream → DMA (S2MM)
-- Data stored in PS DDR
+* AXI4-Stream → DMA (S2MM)
+* Receives **128-bit stream** (4 samples per clock)
+* Stores data in PS DDR memory
 
 Configuration:
-- Frame size: 512
-- Buffers: 16
+
+* Frame size: 512 samples
+* nFrames: configurable (validated up to 1024)
 
 ---
 
-### Processing Pipeline
+## Data Format
 
-DMA → uint64[512]  
-→ unpack real/imag  
-→ convert to complex  
-→ RMS + peak detection  
+### Raw DMA Data
+
+* Packed complex samples
+* 16-bit real + 16-bit imag per sample
+* 4 samples per 128-bit word
+
+---
+
+### Processing Representation
+
+Data is unpacked and reshaped into:
+
+```text
+[FrameSize x nFrames x nTriggers]
+```
+
+or, for processing purposes,
+
+```text
+[FrameSize x nFrames]
+```
+
+representing a single DPW.
+
+---
+
+## Processing Pipeline (Current)
+
+```text
+DMA
+    ↓
+Unpack samples (I/Q separation)
+    ↓
+Convert to complex representation
+    ↓
+Reshape into DPW matrix
+    ↓
+Processing Path Selection
+
+    Path A:
+        Polyphase Filter Bank (PFB)
+            ↓
+        Power Spectrum
+
+    Path B:
+        FFT
+            ↓
+        Power Spectrum
+
+    Path C:
+        FrFT
+            ↓
+        Mean Power Spectrum
+
+    ↓
+Visualization / Analysis
+```
+
+---
+
+## FrFT Processing Status
+
+A first FrFT processing implementation has been integrated into the PS subsystem.
+
+### Processing Flow
+
+```text
+DPW [512 x nFrames]
+        ↓
+Halfband Interpolation (2x)
+        ↓
+FrFT Coefficient Generation
+        ↓
+DPW-Aware FrFT Processing
+        ↓
+Mean Power Spectrum
+```
+
+### Software Structure
+
+```text
+codegen_fracFdpw/
+│
+├── fracF_init.m
+├── fracF_dpw.m
+├── TBc_fracFdpw.m
+└── TBm_fracFdpw.slx
+```
+
+### Validation Completed
+
+* DPW-aware FrFT implementation created
+* Verified against original `fracF_cg`
+* Bit-identical equivalence achieved
+* MATLAB testbench (TBc) created
+* Simulink model testbench (TBm) created
+* TBc ↔ TBm comparison automated
+* Bit-identical TBc ↔ TBm validation achieved
+* Standalone subsystem code generation validated
+* RFSoC PS integration completed
+
+### Current Status
+
+The implementation is functionally correct and integrated into the RFSoC processing chain.
+
+Current work is focused on:
+
+* Performance characterization
+* FrFT parameter optimization
+* Realistic pulse processing scenarios
+
+### Open Technical Questions
+
+The matched-order formulation used in the SPL simulations assumed:
+
+```text
+Observation Window = Pulse Duration
+```
+
+The receiver currently operates under a different condition:
+
+```text
+Observation Window < Pulse Duration
+```
+
+where only a portion of the pulse is processed by the FrFT.
+
+Additional investigation is required to determine:
+
+* Optimal FrFT order for partial-pulse observations
+* Practical DPW sizes
+* Trade-off between concentration and processing load
+* Deviation from idealized SPL simulation conditions
+
+### Current Limitations
+
+* Coefficients are regenerated every execution
+* No coefficient caching implemented
+* No NEON-specific optimization
+* Generated FFT kernels are used
+* Performance scales strongly with DPW size
+
+---
+
+## Validation Support
+
+Uses counter-based validation:
+
+* Real part → sample counter
+* Imag part → frame index
+
+Enables verification of:
+
+* Data continuity
+* Frame alignment
+* Correct ordering from DMA
 
 ---
 
 ## Execution Model
 
-- Event-driven (DMA trigger)
-- No buffering queue
-- Frames may be dropped
+* Triggered (event-based)
+* Burst capture (DPW)
+* Not continuous real-time streaming
 
 ---
 
 ## Performance Notes
 
-- Bottleneck: unpacking + conversion
-- Cannot sustain full-rate input
+Current implementation prioritizes correctness and validation over optimization.
+
+Observations from RFSoC integration:
+
+* FrFT processing successfully executes on the RFSoC PS
+* nFrames = 64 executes responsively
+* nFrames = 1024 remains computationally expensive
+* Processing load scales approximately linearly with DPW size
+* Code generation and subsystem integration have been validated
+
+Current optimization candidates:
+
+* Coefficient caching when FrFT order remains unchanged
+* NEON vectorization
+* Alternative FFT implementations
+* DPW size optimization
 
 ---
 
-## Interaction with PL
+## Role in System
 
-### Tx Control
-- Low-rate trigger (~Hz)
-- Starts burst generation
+The PS currently serves as:
 
-### Rx Data
-- Continuous high-rate stream
+* Control interface
+* Data acquisition manager
+* Signal processing platform
+* Algorithm development and validation environment
+
+Current processing capabilities include:
+
+* PFB-based spectral analysis
+* FFT-based spectral analysis
+* FrFT-based spectral analysis
 
 ---
 
 ## Future Work
 
-- Replace processing with FrFT
-- NEON optimization
-- Throughput improvements
+### FrFT
+
+* Matched-order optimization for realistic pulse captures
+* Performance profiling on RFSoC PS
+* Coefficient caching
+* NEON optimization
+* Detection processing after FrFT concentration
+
+### System
+
+* Timestamp integration
+* UDP streaming
+* Metadata extraction
+* Migration of computationally intensive functions to PL where appropriate
 
 ---
 
 ## 🔗 Related Components
 
-- [🏠 Project Home](../README.md)
-- [PL Tx Subsystem](pl_tx_subsystem.md)
-- [PL Rx Subsystem](pl_rx_subsystem.md)
+* [🏠 Project Home](../README.md)
+* [PL Tx Subsystem](pl_tx_subsystem.md)
+* [PL Rx Subsystem](pl_rx_subsystem.md)

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resources/project/d5dEC3kotuZeerJ4IRjJh3LU3nM/jCxeCZZX-Z1DLQ1xfH3hIxhR958p.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="checkCounterSamples.m" type="File"/>

resources/project/qaw0eS1zuuY1ar9TdPn1GMfrjbQ/0lzvy0CH3x8yVh_vgLFn8eKBrWEp.xml

@@ -1,2 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<Info location="capture_block" type="File"/>

resources/project/qaw0eS1zuuY1ar9TdPn1GMfrjbQ/9lwM0dX3iyjMhadwFjZ2rmFpFrEp.xml

@@ -1,2 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<Info location="frft_codegen" type="File"/>

resources/project/qaw0eS1zuuY1ar9TdPn1GMfrjbQ/F2x-oreEzd1RuWtdF_H3bxSqbsMp.xml

@@ -1,2 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<Info location="bypass_block" type="File"/>

resources/project/qaw0eS1zuuY1ar9TdPn1GMfrjbQ/LpvpJ1uloVvE37aexyCWfqNpR8Ed.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info/>

resources/project/qaw0eS1zuuY1ar9TdPn1GMfrjbQ/LpvpJ1uloVvE37aexyCWfqNpR8Ep.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="block_pulsegen" type="File"/>

resources/project/qaw0eS1zuuY1ar9TdPn1GMfrjbQ/MEnu9bsvaE1ht88eLRvHOJK-Wu0p.xml

@@ -1,2 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<Info location="pulsegen_block" type="File"/>

resources/project/qaw0eS1zuuY1ar9TdPn1GMfrjbQ/QuVfFK49N05REJIAYZLQasz_VuMd.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info/>

resources/project/qaw0eS1zuuY1ar9TdPn1GMfrjbQ/QuVfFK49N05REJIAYZLQasz_VuMp.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="block_capture" type="File"/>