docs: update documentation for capture redesign and validation

changed pulseWidth to pulseT.

README.md

@@ -4,81 +4,76 @@
 
 This project is based on the RFSoC SoC Blockset reference design, adapted as a prototype for a Radar Electronic Support Measures (R-ESM) receiver.
 
-### Current Status
+The system implements a high-throughput signal chain in the FPGA (PL) and performs frame-based processing in the processor (PS).
 
-- Tx subsystem: simple tone generator (to be replaced by LFM pulse generator)
+---
-- Rx subsystem: fully functional channelizer pipeline (PFB-based)
+
-- PL → PS interface: AXI4-Stream + DMA working
+## Current Status
-- PS processing: frame-based algorithm (RMS + peak detection)
+
+- Tx subsystem: LFM pulse generator (DDS-based, complex output)
+- Rx subsystem: fully functional channelizer pipeline (PFB-based) or bypass
+- PL → PS interface: AXI4-Stream + DMA operational
+- PS processing: frame-based algorithm on a Data Process Window (DPW)
 
 ---
 
 ## System Architecture
 
-ADC → Channelizer (PFB, 512 bins)
+Tx (PL)  
-→ FFT_Capture (frame control)
+→ Waveform Generator (LFM / CW / Pulsed)  
-→ FIFO Serializer (4 FIFOs → 1 stream)
+→ DAC  
-→ AXI4-Stream (uint64)
+→ RF Loopback / Input  
-→ DMA (S2MM)
+
-→ PS Memory
+Rx (PL)   
-→ Processor Algorithm (frame-based)
+→ ADC  
+→ Channelizer (PFB, 512 bins) / Bypass / Counter  
+→ Capture (frame control)  
+→ AXI4-Stream (128-bit, 4 samples/clock)  
+→ DMA (S2MM)  
+→ PS Memory  
+→ Processor Algorithm
+
+Post Processing (PS)  
+→ Triggered Capture  
+→ Sample Unpacking (I/Q)  
+→ Data Reshaping → [FrameSize x nFrames x nTriggers]  
+→ Host Communication / Processing / Visualization
+→ One DPW is a windows of FrameSize x nFrames samples
 
 ---
 
 ## Key Parameters
 
-- ADC Sampling Rate: 4096 MSPS
+- ADC Sampling Rate: 4096 MSPS  
-- Decimation: 8
+- Decimation: 8  
-- Effective BW: 512 MHz
+- Effective BW: 512 MHz  
-- Channels (FFT size): 512
+- Channels (FFT size): 512  
-- Samples per clock: 4
+- Samples per clock: 4  
-- FPGA clock: 128 MHz
+- FPGA clock: 128 MHz  
-- Frame size (PS): 512 samples
+- Frame size (PS): 512 samples  
 
 ---
 
-## DMA (PL → PS)
+## 📚 Documentation
 
-- Data type: uint64
+### FPGA (PL)
-- Frame size: 512
-- Buffers: 16
-- Memory: PS DDR
 
-Each TLAST corresponds to one DMA frame.
+- [Tx Subsystem (Pulse Generator)](docs/pl_tx_subsystem.md)
+- [Rx Subsystem (Channelizer)](docs/pl_rx_subsystem.md)
+
+### Processor (PS)
+
+- [PS Subsystem](docs/ps_subsystem.md)
 
 ---
 
-## Processor (PS)
+## System Flow
 
-- Event-driven execution (triggered by DMA)
+Tx → Rx → PS
-- No task queueing
-- Frames may be dropped if processing is slower than input rate
 
----
+- Tx generates waveform  
-
+- Rx captures and channelizes  
-## Data Path in PS
+- PS processes frames  
-
-- Stream Read → uint64[512]
-- Bit extraction → real/imag
-- Conversion → complex vector
-- Processing → RMS + peak detection
-
----
-
-## Performance Notes
-
-- Bottleneck: unpacking + type conversion
-- PS cannot keep up with full-rate stream
-- Frames are skipped under load
-
----
-
-## FrFT Integration Plan
-
-- Replace Processor Algorithm with FrFT
-- Keep all other components unchanged
-- Input: complex single [512x1]
-- Accept dropped frames initially
 
 ---
 

docs/pl_rx_subsystem.md

@@ -0,0 +1,144 @@
+# 📡 PL Rx Subsystem (Channelizer)
+
+[🏠 Project Home](../README.md)
+
+---
+
+## Overview
+
+The Rx subsystem implements a **polyphase filter bank (PFB) channelizer** followed by FFT processing, a **bypass path**, and a **multi-frame capture pipeline**.
+
+It converts wideband ADC input into frequency-domain channels (or raw samples via bypass) and streams the result to the PS.
+
+---
+
+## Architecture
+
+### Channelizer Path (default)
+
+ADC  
+ ↓  
+PFB Channelizer (Decimation + Filtering)  
+ ↓  
+FFT (512 bins)  
+ ↓  
+Capture (frame control)  
+ ↓  
+AXI4-Stream (128-bit, 4 samples/clock)  
+ ↓  
+DMA
+
+---
+
+### Bypass Path (Debug / Raw Data)
+
+ADC  
+ ↓  
+Bypass Path  
+ ↓  
+Capture (frame control)  
+ ↓  
+AXI4-Stream (128-bit, 4 samples/clock)  
+ ↓  
+DMA
+
+---
+
+## Capture Pipeline
+
+- Multi-frame acquisition (configurable nFrames)
+- Frame size: 512 samples
+- Supports asynchronous capture start (not frame-aligned)
+- TLAST asserted at frame boundaries
+
+### Behavior
+
+- First frame may be partial
+- Frames may contain ≤ 2 frame indices (expected)
+- DPW spans nFrames frames but covers nFrames + 1 frame regions
+
+---
+
+## Processing Chain (Channelizer Mode)
+
+### ADC Input
+- Sampling rate: 4096 MSPS
+- Data type: **fixdt(1,16,15)** (Q1.15)
+
+### PFB Channelizer
+- Decimation: 8
+- Effective bandwidth: 512 MHz
+
+### FFT
+- Size: 512
+- Produces frequency bins
+
+### Capture
+- Defines frame boundaries (512 samples)
+- Generates TLAST
+
+---
+
+## Numeric Format and Scaling
+
+### System Standardization
+
+- End-to-end Q1.15 (**fixdt(1,16,15)**)
+
+### Channelizer Output Scaling
+
+- Native: **sFix25_En23**
+- Quantized to: **fixdt(1,16,15)** (round + saturate)
+
+---
+
+## Data Packing (Updated)
+
+- 4 samples per clock
+- Each sample: complex (16-bit real + 16-bit imag)
+- Packed into **128-bit AXI4-Stream word**
+
+Benefits:
+- Matches datapath parallelism
+- Efficient DMA transfers
+- Eliminates need for serializer stage
+
+---
+
+## AXI4-Stream Output
+
+- Width: 128 bits
+- Contains 4 complex samples per cycle
+- TLAST = frame boundary
+
+---
+
+## Debug / Validation Features
+
+A counter-based debug mode is implemented:
+
+- Real part → sample counter (0..511)
+- Imag part → frame index
+
+Used to validate:
+- Sample continuity
+- Frame boundaries
+- DMA ordering and integrity
+
+---
+
+## Key Characteristics
+
+- Fully streaming pipeline
+- Deterministic latency
+- High throughput (4 samples/clock)
+- Dual-mode operation (channelizer / bypass)
+- Validated up to nFrames = 1024
+
+---
+
+## 🔗 Related Components
+
+- [🏠 Project Home](../README.md)
+- [PL Tx Subsystem](pl_tx_subsystem.md)
+- [PS Subsystem](ps_subsystem.md)

docs/pl_tx_subsystem.md

@@ -0,0 +1,177 @@
+# 📡 PL Tx Subsystem (Pulse & Continuous LFM Generator)
+
+[🏠 Project Home](../README.md)
+
+---
+
+## Overview
+
+The Tx subsystem implements a **pulse-based and continuous Linear Frequency Modulated (LFM) chirp generator** using a DDS/NCO architecture in the FPGA (PL).
+
+The generator produces **complex baseband output**:
+
+x[n] = exp(j·φ[n])
+
+and operates deterministically in the PL after a trigger from the PS.
+
+---
+
+## Architecture
+
+TxPulseStart (PS)
+        ↓
+pulse_gen_ctrl (FSM)
+        ↓
+   tx_active
+        ↓
+Phase Increment Logic
+        ↓
+      NCO (DDS)
+        ↓
+   Complex Output (I/Q)
+
+---
+
+## Operating Modes
+
+The subsystem now supports multiple Tx modes:
+
+### 1. Pulsed LFM (default)
+
+- Chirp generated only during pulse window
+- Phase resets at each pulse start
+- Standard radar burst operation
+
+---
+
+### 2. CW Mode (Continuous Wave)
+
+- `tx_active = 1` continuously
+- Generates a single-tone output
+- Achieved by setting constant phase increment
+
+---
+
+### 3. Continuous LFM (Workaround Implementation)
+
+- `tx_active` forced HIGH continuously  
+- A **1-cycle LOW pulse** is inserted periodically  
+- This LOW→HIGH transition **resets the NCO**
+
+Result:
+- Continuous chirp
+- Bounded bandwidth
+- Periodic repetition of LFM
+
+---
+
+## Chirp Generation Principle
+
+The chirp is generated using a second-order phase accumulator:
+
+Δφ[n] = Δφ[n−1] + step  
+φ[n]  = φ[n−1] + Δφ[n]
+
+This results in a linear frequency sweep.
+
+---
+
+## Parameterization (PS → PL)
+
+Inputs:
+
+- Center frequency: Fc  
+- Bandwidth: B  
+- Pulse width: N (samples)
+
+Derived internally:
+
+f_start = Fc − B/2  
+step    = B / (N − 1)
+
+These values are converted to DDS phase increments before being written to PL registers.
+
+---
+
+## Pulse Timing (FSM)
+
+States:
+
+- IDLE: waits for trigger and latches parameters  
+- ACTIVE: generates pulses  
+- DONE: waits for trigger reset  
+
+---
+
+## Timing Behavior
+
+### Pulsed Mode
+
+|<------ PRI ------>|
+|<-- pulse -->| idle |
+
+- tx_active = 1 → chirp output  
+- tx_active = 0 → output zero  
+
+---
+
+### Continuous LFM Mode
+
+tx_active behavior:
+
+1 1 1 1 1 0 1 1 1 1 ...
+
+- 1-cycle LOW inserted at end of chirp period  
+- Rising edge resets NCO  
+- Defines chirp repetition interval  
+
+---
+
+## CW / Continuous LFM Implementation Details
+
+- CW mode bypasses FSM output
+- A dedicated counter generates periodic reset pulses
+- Reset timing is based on `pulse_width_cycles`
+
+Important:
+
+- Reset pulse is exactly **1 clock cycle**
+- Ensures deterministic NCO restart
+- Decoupled from PRI/FSM timing
+
+---
+
+## Burst Trigger (PS Interaction)
+
+- Controlled via TxPulseStart (memory-mapped register)
+- Rising edge triggers burst
+- PL runs autonomously afterward
+
+---
+
+## Key Characteristics
+
+- Deterministic timing (128 MHz)
+- Efficient DDS (adder-based)
+- Complex output (I/Q)
+- Supports:
+  - Pulsed radar mode
+  - Continuous wave (CW)
+  - Continuous LFM (periodic chirp)
+
+---
+
+## Design Notes
+
+- FSM controls **timing (when to transmit)**
+- NCO controls **frequency evolution**
+- Continuous LFM implemented via **tx_active edge reuse**
+- Minimal hardware overhead (no additional NCO logic)
+
+---
+
+## 🔗 Related Components
+
+- [🏠 Project Home](../README.md)
+- [PL Rx Subsystem](pl_rx_subsystem.md)
+- [PS Subsystem](ps_subsystem.md)

docs/ps_subsystem.md

@@ -0,0 +1,140 @@
+# 🧠 PS Subsystem (Control + Capture + Processing)
+
+[🏠 Project Home](../README.md)
+
+---
+
+## Overview
+
+The PS subsystem is responsible for:
+
+- System initialization
+- Configuring PL subsystems
+- Triggering captures
+- Receiving data via DMA
+- Preparing data for processing and visualization
+
+The current implementation acts as a **placeholder for post-processing**, focusing on reliable data acquisition and host interaction.
+
+---
+
+## Responsibilities
+
+### Control & Initialization
+
+- Configure PL parameters:
+  - Tx waveform configuration
+  - Capture parameters (nFrames, etc.)
+- Initialize DMA and memory buffers
+- Manage system startup
+
+---
+
+### Trigger & Capture
+
+- Generates capture trigger (software-controlled)
+- Controls DPW acquisition timing
+- Each trigger initiates one DPW capture
+
+---
+
+### DMA Handling
+
+- AXI4-Stream → DMA (S2MM)
+- Receives **128-bit stream** (4 samples per clock)
+- Stores data in PS DDR memory
+
+Configuration:
+- Frame size: 512 samples
+- nFrames: configurable (validated up to 1024)
+
+---
+
+## Data Format
+
+### Raw DMA Data
+
+- Packed complex samples
+- 16-bit real + 16-bit imag per sample
+- 4 samples per 128-bit word
+
+---
+
+### Processing Representation
+
+Data is unpacked and reshaped into:
+
+```
+[FrameSize x nFrames x nTriggers]
+```
+
+---
+
+## Processing Pipeline (Current)
+
+DMA  
+→ Unpack samples (I/Q separation)  
+→ Convert to complex representation  
+→ Reshape into 3D structure  
+→ Visualization / basic analysis  
+
+---
+
+## Validation Support
+
+Uses counter-based validation:
+
+- Real part → sample counter
+- Imag part → frame index
+
+Enables verification of:
+
+- Data continuity
+- Frame alignment
+- Correct ordering from DMA
+
+---
+
+## Execution Model
+
+- Triggered (event-based)
+- Burst capture (DPW)
+- Not continuous real-time streaming
+
+---
+
+## Performance Notes
+
+- Designed for correctness and validation (not optimized)
+- Bottleneck: unpacking + data movement
+- Full-rate continuous processing not supported
+
+---
+
+## Role in System
+
+The PS currently serves as:
+
+- Control interface
+- Data acquisition manager
+- Pre-processing stage
+
+Future implementations will replace the current processing with advanced algorithms (e.g., FrFT).
+
+---
+
+## Future Work
+
+- FrFT-based processing
+- Timestamp integration
+- UDP streaming
+- Optimization (NEON / vectorization)
+- Metadata extraction (move complexity to PL)
+
+---
+
+## 🔗 Related Components
+
+- [🏠 Project Home](../README.md)
+- [PL Tx Subsystem](pl_tx_subsystem.md)
+- [PL Rx Subsystem](pl_rx_subsystem.md)

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resources/project/QuVfFK49N05REJIAYZLQasz_VuM/G0MCWfbLWGDEK-XGehbFPxgX67gd.xml

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resources/project/QuVfFK49N05REJIAYZLQasz_VuM/G0MCWfbLWGDEK-XGehbFPxgX67gp.xml

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resources/project/QuVfFK49N05REJIAYZLQasz_VuM/Xx0UDP9sUzEZe711HBEUtl4YraYp.xml

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resources/project/bMFzsIHr-EVKQIO2sqeU-274_I8/6ogmP0ZksmbyaUjs5D-G7nePRvod.xml

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resources/project/bMFzsIHr-EVKQIO2sqeU-274_I8/6ogmP0ZksmbyaUjs5D-G7nePRvop.xml

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resources/project/d5dEC3kotuZeerJ4IRjJh3LU3nM/F6I45Jz3Y8Cbk8qxkuAN2aHpqcUp.xml

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resources/project/d5dEC3kotuZeerJ4IRjJh3LU3nM/Sqf9uvnGiYyl02crmP5dcX378Bsd.xml

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+<?xml version="1.0" encoding="UTF-8"?>
+<Info>
+    <Category UUID="FileClassCategory">
+        <Label UUID="design"/>
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resources/project/d5dEC3kotuZeerJ4IRjJh3LU3nM/Sqf9uvnGiYyl02crmP5dcX378Bsp.xml

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resources/project/d5dEC3kotuZeerJ4IRjJh3LU3nM/YcrfchWz89iaifBeF9RcdywvjvAd.xml

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resources/project/d5dEC3kotuZeerJ4IRjJh3LU3nM/YcrfchWz89iaifBeF9RcdywvjvAp.xml

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resources/project/d5dEC3kotuZeerJ4IRjJh3LU3nM/jCxeCZZX-Z1DLQ1xfH3hIxhR958d.xml

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resources/project/d5dEC3kotuZeerJ4IRjJh3LU3nM/jCxeCZZX-Z1DLQ1xfH3hIxhR958p.xml

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resources/project/qaw0eS1zuuY1ar9TdPn1GMfrjbQ/9lwM0dX3iyjMhadwFjZ2rmFpFrEp.xml

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resources/project/qaw0eS1zuuY1ar9TdPn1GMfrjbQ/LpvpJ1uloVvE37aexyCWfqNpR8Ed.xml

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resources/project/qaw0eS1zuuY1ar9TdPn1GMfrjbQ/LpvpJ1uloVvE37aexyCWfqNpR8Ep.xml

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resources/project/qaw0eS1zuuY1ar9TdPn1GMfrjbQ/QuVfFK49N05REJIAYZLQasz_VuMd.xml

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resources/project/qaw0eS1zuuY1ar9TdPn1GMfrjbQ/QuVfFK49N05REJIAYZLQasz_VuMp.xml

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resources/project/qaw0eS1zuuY1ar9TdPn1GMfrjbQ/bMFzsIHr-EVKQIO2sqeU-274_I8p.xml

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resources/project/qaw0eS1zuuY1ar9TdPn1GMfrjbQ/rW25SbP5jRWeIzL7_iMpZrrygYkp.xml

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resources/project/rW25SbP5jRWeIzL7_iMpZrrygYk/8i67CMLFhpgTFLAi_RBlc2P1lI0p.xml

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resources/project/rW25SbP5jRWeIzL7_iMpZrrygYk/XVu9f1ZjVk2AJ99l5f9CAU_dcMEp.xml

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