canisio/Zcu111ResmReceiver
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  • 3c6ae0cfe9 finished organization of init funcions and parameters canisio 2026-04-04 16:05:17 -03:00
  • eb14676581 Oganize preload and init functions and parameters (ongoing) canisio 2026-04-04 15:16:58 -03:00
  • 040834d511 added docs folder to project path. tested remotely. OK canisio 2026-04-03 20:47:13 -03:00
  • a92709b500 Added bypass of channelizer to the documentation canisio 2026-04-02 17:39:01 -03:00
  • 27ec12161c detailed subsystems canisio 2026-04-02 17:36:23 -03:00
  • 5caaa7fd9a updated README canisio 2026-04-02 17:32:03 -03:00
  • ea0ecefae1 Added documentation and updated README canisio 2026-04-02 17:29:24 -03:00
  • e810145620 Pulse Generator TB validated canisio 2026-04-02 17:08:44 -03:00
  • a82aed0d5a Changed NCO to complex on TBm_chirp canisio 2026-04-02 16:43:03 -03:00
  • 62ab58b741 Changed Update parameter subsystem on chirp TB to pulse fc and pulse BW. canisio 2026-04-02 16:28:41 -03:00
  • 8e397fa41e Added draft to TBm_chirp model. Added init function script to testbench canisio 2026-04-02 12:03:59 -03:00
  • 790c2fdb37 added placeholder for chirp block canisio 2026-04-01 12:05:57 -03:00
  • 872fbfcd6e Minor changes canisio 2026-04-01 11:51:59 -03:00
  • 9794b2d540 tested on HW. Bypass ok. canisio 2026-03-31 18:47:13 -03:00
  • b72a8cd616 added time scope to interface canisio 2026-03-31 18:00:27 -03:00
  • f66c3ffd06 Changed interface model to reflect bypass canisio 2026-03-31 17:51:26 -03:00
  • 0c6938bff2 commented initialize register on proc model canisio 2026-03-31 17:25:01 -03:00
  • 66ad6149e6 Added switch and led (physical) canisio 2026-03-31 16:41:27 -03:00
  • a9b4ad9e17 Added bypass toggle via memory mapped register canisio 2026-03-31 16:17:34 -03:00
  • 0ea6881d1e Added bypass to Rx on FPGA. Test OK canisio 2026-03-31 15:55:46 -03:00
  • 278e318715 Added simulink model to testbench bypass funcion (bypass folder) canisio 2026-03-31 14:26:45 -03:00
  • e0765a6afe Added bypass funcion and its testbench (bypass folder) canisio 2026-03-31 14:25:43 -03:00
  • dd70d58f2a Added frtt_codegen folder to the project initialization canisio 2026-03-31 09:19:28 -03:00
  • d8a9e026ff Added testbench for simulink model. Added f0 option to both testbenches canisio 2026-03-30 16:01:46 -03:00
  • 1613ae8ad9 Ran codegen for mex and tested. Working ok canisio 2026-03-30 11:44:31 -03:00
  • 7b04d52204 Added frft functions towards codegen (c code on PS) canisio 2026-03-30 11:16:12 -03:00
  • 30b31509c1 Updated README canisio 2026-03-30 09:30:16 -03:00
  • 10644b0475 added README canisio 2026-03-27 18:41:29 -03:00
  • 43f91b281b Tested on board. Running ok. Updated interface model and added shortcut to it. canisio 2026-03-27 17:52:13 -03:00
  • 89ecf79e61 Added comment os PS system. Info from training says the time-driven tasks are all inside the processor block, except the event driven and the initialize canisio 2026-03-27 17:17:28 -03:00
  • 13263f4f33 Removed one of the channels and respective beamforming on Tx and Rx. Simulation ok. Kept the read registers of the angles as placeholders for future use. canisio 2026-03-27 16:51:41 -03:00
  • 81ca3ee48c Added renamed prj file canisio 2026-03-27 15:52:18 -03:00
  • 2e297e7f07 Rename project and clean tracked files canisio 2026-03-27 15:51:00 -03:00
  • 7c361a9608 Prepare to remove one of the channels. The idea is to transform the beamforming project in a simple wideband detector. canisio 2026-03-27 13:24:50 -03:00
  • 584db6233c - Added utilities for frequency planning - Changed freq plane to: Fs 4096, int/dec 8X, Mixers 768 canisio 2026-03-27 12:50:10 -03:00
  • d5bbdfb435 Changed NCO on AD/DA to 0Hz. Changed language for HDL IP to Verilog. Cleaned up for new soc_prj generation canisio 2026-03-25 18:23:42 -03:00
  • 89c8003f5a Added sw interface model (controls hardware running on board). canisio 2026-03-25 17:21:09 -03:00
  • 7c1292ae5c Added startup function to project (setup HDL tool on it) canisio 2026-03-25 16:15:16 -03:00
  • c86497656b Changed fs to 1024MSPS and added double-sided spectrum visualization. FFT Shifit with two selectors and one concatenate canisio 2026-03-24 18:10:26 -03:00
  • ac2e7bcece Initial canisio 2026-03-24 12:44:45 -03:00