canisio/Zcu111ResmReceiver
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  • 261984b30f update diagram (added Simulink) feature/ps-frft canisio 2026-07-02 16:04:00 -03:00
  • 472dcaf62f diagram update (added PS) canisio 2026-07-02 15:36:04 -03:00
  • 29a5afbf7e updated diagram (PL side ok) canisio 2026-06-26 13:43:42 -03:00
  • 577a816dbf updated diagram canisio 2026-06-26 13:41:24 -03:00
  • 1b56b3c9ca Updated main readme to show the block diagram canisio 2026-06-26 13:15:55 -03:00
  • 4accb84e4a Added block diagram of the system canisio 2026-06-26 13:12:33 -03:00
  • a5990ae650 nFrames reduced to 64. Responsiveness is back. So the FrFT implementation is not optimized on the A53 processor. Nevertheless, peak is not concentrated, I still need to figure out parameters of transform and how to cope with this non-ideal case (real life) canisio 2026-06-26 11:34:02 -03:00
  • c0b4435cd0 updated documentation (PS) canisio 2026-06-11 13:00:23 -03:00
  • 2d668be90f nFrames reduced to 64. Responsiveness is back. So the FrFT implementation is not optimized on the A53 processor. Nevertheless, peak is not concentrated, I still need to figure out parameters of transform and how to cope with this non-ideal case (real life) canisio 2026-06-11 12:43:46 -03:00
  • aba2f02820 Test: remove tunnable a canisio 2026-06-11 12:07:30 -03:00
  • dd79f8692a fracF_DPW integrated to external mode. Running very slow canisio 2026-06-11 11:32:17 -03:00
  • 56d3dd647e FracF_DPW integrated to design. Not validated yet. canisio 2026-06-10 17:16:58 -03:00
  • a37ded1d73 codegen OK! canisio 2026-06-10 16:36:56 -03:00
  • 7dd20a04fa compared both TBc and TBm, results are equivalent (not identical because of interpolation filter) canisio 2026-06-10 16:05:30 -03:00
  • 8f2ae1ec4e Added a LFM matlab script testbench to validate FrFT DPW canisio 2026-06-10 11:46:16 -03:00
  • 4f5ac3b5f3 Organized codegen for fracFdpw. Tested with random input in matlab script. OK canisio 2026-06-10 09:59:18 -03:00
  • 943b582d66 ignore generated files/folders from codegen canisio 2026-06-09 16:28:35 -03:00
  • 2428f5a861 FrFT DPW processing validade in terms of dimensions and code generation canisio 2026-06-09 16:18:00 -03:00
  • f64f4fde31 Added codegen folder and scripts for fracF operating in DPW (matrix) canisio 2026-06-09 16:15:39 -03:00
  • 22c51e1597 FrFT not working (for each error) canisio 2026-06-09 14:54:59 -03:00
  • 23a3503cb1 initialization of pulse center freq. canisio 2026-06-09 10:51:09 -03:00
  • 21c46dc45e removed subfolders codegen_frft canisio 2026-05-22 15:58:53 -03:00
  • 99ffaa1bfc startup funcion adapted to non-vivado machines canisio 2026-05-22 15:42:32 -03:00
  • 48bbb7102a first tests on FrFT canisio 2026-05-22 12:57:30 -03:00
  • b57260583a fft of FrFT block changed from FFTW to auto canisio 2026-05-21 17:30:38 -03:00
  • 8839674480 renamed the scopes to differentiate sim to hw canisio 2026-05-21 17:22:52 -03:00
  • 005d488d79 Added variant subsystem and placeholder for FrFT. Simulation OK. External gives error canisio 2026-05-19 17:19:30 -03:00
  • baedad87fa NEON optimization enabled for C code generation on both proc and interface models canisio 2026-04-30 17:39:17 -03:00
  • 19fd4dfb2d second validation of MeanPowSpec before branch to FrFT. Created slides on interface and tested several combinations of paramters. Resulds within expected. main v2.1 canisio 2026-04-30 12:24:24 -03:00
  • 1622f922f9 MeanPowSpec validated on board canisio 2026-04-29 17:07:10 -03:00
  • 041218aa7f test MeanPowSpec on ZCU111 canisio 2026-04-29 16:35:55 -03:00
  • d9f7798814 Added Mean Power Spectrum calculation on PS canisio 2026-04-29 16:10:21 -03:00
  • 1ab873419e clean version after tagging canisio 2026-04-29 14:11:51 -03:00
  • 65cef793ac Removed RMS and Fmax outputs Formatted top diagrams v2.0 canisio 2026-04-29 11:30:02 -03:00
  • 99c6b62fc6 Added CwMode as toggle switch canisio 2026-04-29 10:44:14 -03:00
  • dc76c69731 added folder "codegen_frft" to the project (it was renamed) canisio 2026-04-29 10:21:17 -03:00
  • 1d0309f060 Merge branch 'feature/capture-redesign': Integrate capture redesign (multi-frame DMA + validation) canisio 2026-04-29 10:15:07 -03:00
  • 19b0513809 docs: update documentation for capture redesign and validation feature/capture-redesign canisio 2026-04-29 10:03:34 -03:00
  • b3ba729f8b Pulsed input LFM tested on board. Appears ok on both channelizer and bypass. canisio 2026-04-28 17:43:45 -03:00
  • c7cb4e770f Simulated with pulsed signal before testing on ZCU111 canisio 2026-04-28 16:31:04 -03:00
  • 6093942ab3 include check scripts to the project. changed pulseWidth to pulseT. canisio 2026-04-28 15:22:03 -03:00
  • edef1dbed3 validation: add checkCounterSamples and verify capture up to 1024 frames on ZCU111 canisio 2026-04-27 18:32:31 -03:00
  • b8d2d6a5dd updated postload funcion to not break when top is unloaded canisio 2026-04-27 12:21:03 -03:00
  • 4216288e2a Removed delays from bypass Removed visualisation from PS DPW visualization and log outside PS (external mode) canisio 2026-04-27 12:09:46 -03:00
  • df335aac1e validation: verified capture pipeline in counter bypass, sine bypass, and sine channelizer modes (nFrames=8) canisio 2026-04-25 12:58:22 -03:00
  • 1ebf8aa076 codegen: increase max identifier length to 64 in soc_rfsoc_proc and gm_soc_rfsoc_top_sw canisio 2026-04-25 11:53:24 -03:00
  • f9a2eff397 validate sine over bypass using a post processing script in the logged data. Added folter post_processing and script checkTimeSamples canisio 2026-04-25 11:28:43 -03:00
  • 2f5a466ace Visualization blocks, rate changed to TsSW/nFrames canisio 2026-04-24 17:31:17 -03:00
  • ff3aa5e89f Revert "Created valid_out for conter input test" canisio 2026-04-24 17:25:45 -03:00
  • a7e710b603 Created valid_out for conter input test canisio 2026-04-24 16:36:13 -03:00
  • c10736a5d7 AXI4-S2Software>Main>Advanced>Interconnect: Data width (bits) changed to 128 canisio 2026-04-24 12:14:14 -03:00
  • 2b7d05b3d9 FPGA Packer: Changed to uint128, changed endianess order of packing (selectors 4,3,2,1) canisio 2026-04-24 11:59:16 -03:00
  • 4cbe3b5699 renamed array plots os gm model canisio 2026-04-24 11:33:15 -03:00
  • bbf87121f0 changed to upper and lower halves after stream read. No difference (only first lane of 4x1 being read) canisio 2026-04-23 15:26:22 -03:00
  • 525a5f65e5 unchecked "enable sample packing" on signal attributes of AXI4-stream to software canisio 2026-04-23 08:53:01 -03:00
  • 9a7a05f450 stream read read only first sample of [4 x 1] bundle canisio 2026-04-22 16:38:16 -03:00
  • 0df1044d13 Input test counter moved to Rx Subsystem canisio 2026-04-22 14:37:28 -03:00
  • f5ec4e6b6e sine and channelizer appear to work on board. Need to move counter to Rx to fully validate sample order canisio 2026-04-22 12:29:13 -03:00
  • 293b0e6c50 Updated memory mapped addresses canisio 2026-04-22 10:45:07 -03:00
  • 9a0404f1a9 4 dalay on the signals of bypass to align test counter to frame start. Appears to be working. Test on board. canisio 2026-04-22 10:30:14 -03:00
  • 6098d86851 problem on the bypass sample counter: if delay sof,eof,vali on FSM input ok for counter but wrong for channelizer canisio 2026-04-21 18:00:44 -03:00
  • 4ad5c3c5ea appear to be working with 4 daley after multi-frame capture. Problem is on visualization, canisio 2026-04-21 16:19:43 -03:00
  • 4b1b94c424 Added counter mode as input, real part = sample counter, imag part = frame counter. Reset on software trigger canisio 2026-04-21 12:25:21 -03:00
  • 78a7d1ae68 updated interface model. Still not working canisio 2026-04-21 10:00:38 -03:00
  • 97d5494781 updated gm_top_sw. Runs on board, but capture is not in sync canisio 2026-04-20 17:10:59 -03:00
  • 7f369d8692 runs on the board. But capture is not in sync canisio 2026-04-20 17:09:57 -03:00
  • 286c464f5a set SoCData as datatype again on the stream read inport (I dont know if this was the problem, but its working again) canisio 2026-04-20 15:04:14 -03:00
  • 91b02cdc79 organized register... stopped working canisio 2026-04-20 11:53:26 -03:00
  • 0b1dc081e5 commented display on PS, before testing in the board canisio 2026-04-20 10:51:08 -03:00
  • d8fe924f6e tests before trying in the board canisio 2026-04-20 10:49:21 -03:00
  • b2ce956f41 Multi-frame capture integrated into full design with trigger-controlled DPW; AXI stream (uint32 [4x1]) and DMA framing aligned; fixed FSM termination condition (no overflow); validated end-to-end (PL→DMA→PS) using counter input for multiple nFrames canisio 2026-04-17 17:03:34 -03:00
  • fc50e71ab5 AXI stream updated to uint32 [4x1] format; samples-per-frame aligned to nFrames×512; PS stream read configured accordingly; single-frame (nFrames=1) validated end-to-end (PL→DMA→PS) with correct unpacking and data integrity canisio 2026-04-17 12:22:12 -03:00
  • ce87190fba If sw side of AXI4-Stream to Software block is set to fixdt(128), frames appear to be arriving correctly on PS. However, reinterpretation is failing when using option "uint32" canisio 2026-04-17 11:33:18 -03:00
  • cb56e78923 changed folder name for all testbench models canisio 2026-04-17 08:31:14 -03:00
  • a3d46a9113 New register MF_nFrames added to PS (initialize and data genearation/capture). Not tested canisio 2026-04-16 17:35:10 -03:00
  • 15f20619b1 MultiFrame camputre PL part integrated (no test, no PS) canisio 2026-04-16 17:25:28 -03:00
  • 88e9df3dbb Multi-frame capture (trigger-controlled DPW) validated in testbench; added 128-bit packer replacing serializer, correct unpacking (SI reinterpret) and frame reconstruction verified (counter + PFB); implemented VALID gating (zero when idle) and AXI-aligned pipelining; nFrames parameterized in TB canisio 2026-04-16 16:44:44 -03:00
  • beb5410390 added visualisation to validate ouput of multiple frames canisio 2026-04-16 11:56:25 -03:00
  • 2b8f8de030 Validation of multiframe on TBm_capture done. canisio 2026-04-15 17:52:09 -03:00
  • 9fd110f451 Replace serializer with 128-bit packer and add MultiFrameCapture (testbench) canisio 2026-04-14 17:56:57 -03:00
  • aad231b55a AXI with 128 bits and no serializer appears to be working canisio 2026-04-14 16:46:18 -03:00
  • 3748b65872 implemented sample packer to construct 128 AXI. Partially working (only bypass works?) canisio 2026-04-14 12:25:01 -03:00
  • d83006c50c Added counter as input for the TBm_capture canisio 2026-04-14 10:32:02 -03:00
  • 5e5bba3ce6 Stable 16-bit Q1.15 Rx chain before AXI width upgrade canisio 2026-04-14 09:25:01 -03:00
  • ccc6b9cd73 Validate 16-bit Q1.15 Rx chain (baseline, partial validation) canisio 2026-04-13 17:47:08 -03:00
  • f221e14c2c updated Rx documentation canisio 2026-04-13 16:47:42 -03:00
  • a01186484e Rx: standardize to Q1.15 and reduce channelizer output to 32-bit complex canisio 2026-04-13 16:47:25 -03:00
  • 4241699c3d TBm_caputre. changed PFB internals and output datatype canisio 2026-04-09 12:43:32 -03:00
  • d4e53a67ee Stable single frame (512 samples) baseline before capture redesign v1.1 canisio 2026-04-09 09:27:44 -03:00
  • 2e570cee8b Created folder and test bench model for new capture block. Copied from current version. canisio 2026-04-08 15:50:59 -03:00
  • f8edb31dc2 updated doc: Tx subsystem canisio 2026-04-08 15:04:15 -03:00
  • 520a37f520 CW mode integrated to design canisio 2026-04-08 15:00:47 -03:00
  • cd91e3066b added CW mode (with LFM) to the chirp block (TB, not integrated yet) canisio 2026-04-08 12:19:03 -03:00
  • 5a3bc8891d cleaned up log signals (still not working) canisio 2026-04-07 09:26:50 -03:00
  • fdde9ec62b Initiliaze funcion back to 1 (in the toggle registers). Still not working canisio 2026-04-06 17:39:05 -03:00
  • 84b795203a pulse generator integrated but not working canisio 2026-04-06 16:16:42 -03:00
  • ada7e324cd Fixed register address on "update parameters" canisio 2026-04-06 15:15:55 -03:00
  • 7813d9744c Modified PS part and interface towards pulse generation integration canisio 2026-04-06 12:26:06 -03:00
  • 05b74503dc Fixed init callback for pulse gen testbench v1.0 canisio 2026-04-06 10:45:21 -03:00
  • 72b9a34db9 Ready to move from sine to pulse generator (Tx Subsystem) canisio 2026-04-06 10:23:23 -03:00