canisio

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• Joined on 2026-03-24

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canisio pushed to main at canisio/Zcu111ResmReceiver 2026-03-25 18:25:27 -03:00

d5bbdfb435 Changed NCO on AD/DA to 0Hz. Changed language for HDL IP to Verilog. Cleaned up for new soc_prj generation

canisio pushed to main at canisio/Zcu111ResmReceiver 2026-03-25 17:21:12 -03:00

89c8003f5a Added sw interface model (controls hardware running on board).

canisio pushed to main at canisio/Zcu111ResmReceiver 2026-03-25 16:15:20 -03:00

7c1292ae5c Added startup function to project (setup HDL tool on it)

canisio pushed to main at canisio/Zcu111ResmReceiver 2026-03-24 18:10:33 -03:00

c86497656b Changed fs to 1024MSPS and added double-sided spectrum visualization. FFT Shifit with two selectors and one concatenate

canisio pushed to main at canisio/Zcu111ResmReceiver 2026-03-24 12:45:06 -03:00

ac2e7bcece Initial

canisio created branch main in canisio/Zcu111ResmReceiver 2026-03-24 12:45:06 -03:00

canisio created repository canisio/Zcu111ResmReceiver 2026-03-24 12:43:25 -03:00