Block a user
9a0404f1a9
4 dalay on the signals of bypass to align test counter to frame start. Appears to be working. Test on board.
6098d86851
problem on the bypass sample counter: if delay sof,eof,vali on FSM input ok for counter but wrong for channelizer
4ad5c3c5ea
appear to be working with 4 daley after multi-frame capture. Problem is on visualization,
4b1b94c424
Added counter mode as input, real part = sample counter, imag part = frame counter. Reset on software trigger
286c464f5a
set SoCData as datatype again on the stream read inport (I dont know if this was the problem, but its working again)
b2ce956f41
Multi-frame capture integrated into full design with trigger-controlled DPW; AXI stream (uint32 [4x1]) and DMA framing aligned; fixed FSM termination condition (no overflow); validated end-to-end (PL→DMA→PS) using counter input for multiple nFrames
fc50e71ab5
AXI stream updated to uint32 [4x1] format; samples-per-frame aligned to nFrames×512; PS stream read configured accordingly; single-frame (nFrames=1) validated end-to-end (PL→DMA→PS) with correct unpacking and data integrity
ce87190fba
If sw side of AXI4-Stream to Software block is set to fixdt(128), frames appear to be arriving correctly on PS. However, reinterpretation is failing when using option "uint32"
a3d46a9113
New register MF_nFrames added to PS (initialize and data genearation/capture). Not tested
88e9df3dbb
Multi-frame capture (trigger-controlled DPW) validated in testbench; added 128-bit packer replacing serializer, correct unpacking (SI reinterpret) and frame reconstruction verified (counter + PFB); implemented VALID gating (zero when idle) and AXI-aligned pipelining; nFrames parameterized in TB