canisio
c7cb4e770f
Simulated with pulsed signal before testing on ZCU111
2026-04-28 16:31:04 -03:00
canisio
6093942ab3
include check scripts to the project.
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changed pulseWidth to pulseT.
2026-04-28 15:22:03 -03:00
canisio
edef1dbed3
validation: add checkCounterSamples and verify capture up to 1024 frames on ZCU111
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Created checkCounterSamples.m to validate sample continuity, counter wraps,
and frame index progression. Verified counter bypass, sine bypass, and
channelizer modes up to nFrames=1024 across 10 DPWs on ZCU111.
2026-04-27 18:32:31 -03:00
canisio
b8d2d6a5dd
updated postload funcion to not break when top is unloaded
2026-04-27 12:21:03 -03:00
canisio
4216288e2a
Removed delays from bypass
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Removed visualisation from PS
DPW visualization and log outside PS (external mode)
2026-04-27 12:09:46 -03:00
canisio
df335aac1e
validation: verified capture pipeline in counter bypass, sine bypass, and sine channelizer modes (nFrames=8)
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Validated end-to-end data integrity and visualization across all modes.
2026-04-25 12:58:22 -03:00
canisio
1ebf8aa076
codegen: increase max identifier length to 64 in soc_rfsoc_proc and gm_soc_rfsoc_top_sw
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Updated Configuration Parameters (Code Generation -> Identifiers) in both
soc_rfsoc_proc and parent model gm_soc_rfsoc_top_sw to set Maximum identifier
length from 31 to 64. This avoids truncation of generated identifiers, reduces
risk of name collisions, and ensures consistency across referenced models to
prevent build mismatches.
2026-04-25 11:53:24 -03:00
canisio
f9a2eff397
validate sine over bypass using a post processing script in the logged data. Added folter post_processing and script checkTimeSamples
2026-04-25 11:28:43 -03:00
canisio
2f5a466ace
Visualization blocks, rate changed to TsSW/nFrames
2026-04-24 17:31:17 -03:00
canisio
ff3aa5e89f
Revert "Created valid_out for conter input test"
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This reverts commit a7e710b603
2026-04-24 17:25:45 -03:00
canisio
a7e710b603
Created valid_out for conter input test
2026-04-24 16:36:13 -03:00
canisio
c10736a5d7
AXI4-S2Software>Main>Advanced>Interconnect: Data width (bits) changed to 128
2026-04-24 12:14:14 -03:00
canisio
2b7d05b3d9
FPGA Packer: Changed to uint128, changed endianess order of packing (selectors 4,3,2,1)
2026-04-24 11:59:16 -03:00
canisio
4cbe3b5699
renamed array plots os gm model
2026-04-24 11:33:15 -03:00
canisio
bbf87121f0
changed to upper and lower halves after stream read. No difference (only first lane of 4x1 being read)
2026-04-23 15:26:22 -03:00
canisio
525a5f65e5
unchecked "enable sample packing" on signal attributes of AXI4-stream to software
2026-04-23 08:53:01 -03:00
canisio
9a7a05f450
stream read read only first sample of [4 x 1] bundle
2026-04-22 16:38:16 -03:00
canisio
0df1044d13
Input test counter moved to Rx Subsystem
2026-04-22 14:37:28 -03:00
canisio
f5ec4e6b6e
sine and channelizer appear to work on board. Need to move counter to Rx to fully validate sample order
2026-04-22 12:29:13 -03:00
canisio
293b0e6c50
Updated memory mapped addresses
2026-04-22 10:45:07 -03:00
canisio
9a0404f1a9
4 dalay on the signals of bypass to align test counter to frame start. Appears to be working. Test on board.
2026-04-22 10:30:14 -03:00
canisio
6098d86851
problem on the bypass sample counter: if delay sof,eof,vali on FSM input ok for counter but wrong for channelizer
2026-04-21 18:00:44 -03:00
canisio
4ad5c3c5ea
appear to be working with 4 daley after multi-frame capture. Problem is on visualization,
2026-04-21 16:19:43 -03:00
canisio
4b1b94c424
Added counter mode as input, real part = sample counter, imag part = frame counter. Reset on software trigger
2026-04-21 12:25:21 -03:00
canisio
78a7d1ae68
updated interface model. Still not working
2026-04-21 10:00:38 -03:00
canisio
97d5494781
updated gm_top_sw. Runs on board, but capture is not in sync
2026-04-20 17:10:59 -03:00
canisio
7f369d8692
runs on the board. But capture is not in sync
2026-04-20 17:09:57 -03:00
canisio
286c464f5a
set SoCData as datatype again on the stream read inport (I dont know if this was the problem, but its working again)
2026-04-20 15:04:14 -03:00
canisio
91b02cdc79
organized register... stopped working
2026-04-20 11:53:26 -03:00
canisio
0b1dc081e5
commented display on PS, before testing in the board
2026-04-20 10:51:08 -03:00
canisio
d8fe924f6e
tests before trying in the board
2026-04-20 10:49:21 -03:00
canisio
b2ce956f41
Multi-frame capture integrated into full design with trigger-controlled DPW; AXI stream (uint32 [4x1]) and DMA framing aligned; fixed FSM termination condition (no overflow); validated end-to-end (PL→DMA→PS) using counter input for multiple nFrames
2026-04-17 17:03:34 -03:00
canisio
fc50e71ab5
AXI stream updated to uint32 [4x1] format; samples-per-frame aligned to nFrames×512; PS stream read configured accordingly; single-frame (nFrames=1) validated end-to-end (PL→DMA→PS) with correct unpacking and data integrity
2026-04-17 12:22:12 -03:00
canisio
ce87190fba
If sw side of AXI4-Stream to Software block is set to fixdt(128), frames appear to be arriving correctly on PS. However, reinterpretation is failing when using option "uint32"
2026-04-17 11:33:18 -03:00
canisio
cb56e78923
changed folder name for all testbench models
2026-04-17 08:31:14 -03:00
canisio
a3d46a9113
New register MF_nFrames added to PS (initialize and data genearation/capture). Not tested
2026-04-16 17:35:10 -03:00
canisio
15f20619b1
MultiFrame camputre PL part integrated (no test, no PS)
2026-04-16 17:25:28 -03:00
canisio
88e9df3dbb
Multi-frame capture (trigger-controlled DPW) validated in testbench; added 128-bit packer replacing serializer, correct unpacking (SI reinterpret) and frame reconstruction verified (counter + PFB); implemented VALID gating (zero when idle) and AXI-aligned pipelining; nFrames parameterized in TB
2026-04-16 16:44:44 -03:00
canisio
beb5410390
added visualisation to validate ouput of multiple frames
2026-04-16 11:56:25 -03:00
canisio
2b8f8de030
Validation of multiframe on TBm_capture done.
2026-04-15 17:52:09 -03:00
canisio
9fd110f451
Replace serializer with 128-bit packer and add MultiFrameCapture (testbench)
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Removed FIFO serializer and implemented 128-bit AXI packing (4 samples/beat)
Added initial MultiFrameCapture FSM
Validated with counter input
Sine/channelizer validation pending (frame interpretation update needed)
2026-04-14 17:56:57 -03:00
canisio
aad231b55a
AXI with 128 bits and no serializer appears to be working
2026-04-14 16:46:18 -03:00
canisio
3748b65872
implemented sample packer to construct 128 AXI. Partially working (only bypass works?)
2026-04-14 12:25:01 -03:00
canisio
d83006c50c
Added counter as input for the TBm_capture
2026-04-14 10:32:02 -03:00
canisio
5e5bba3ce6
Stable 16-bit Q1.15 Rx chain before AXI width upgrade
2026-04-14 09:25:01 -03:00
canisio
ccc6b9cd73
Validate 16-bit Q1.15 Rx chain (baseline, partial validation)
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Standardized ADC/DAC and channelizer input to fixdt(1,16,15)
Rescaled channelizer output from sFix25_En23 to 16-bit complex
Verified channelizer path and spectrum behavior in full simulation
Bypass path and datatype tuning (coefficients/output) pending validation
2026-04-13 17:47:08 -03:00
canisio
f221e14c2c
updated Rx documentation
2026-04-13 16:47:42 -03:00
canisio
a01186484e
Rx: standardize to Q1.15 and reduce channelizer output to 32-bit complex
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- ADC/DAC set to fixdt(1,16,15)
- Channelizer output scaled from sFix25_En23 to Q1.15
- Data width reduced from 50b to 32b
- Validated channelizer and bypass paths
Model: TBm_capture.slx
2026-04-13 16:47:25 -03:00
canisio
4241699c3d
TBm_caputre. changed PFB internals and output datatype
2026-04-09 12:43:32 -03:00
canisio
d4e53a67ee
Stable single frame (512 samples) baseline before capture redesign
2026-04-09 09:27:44 -03:00
