canisio
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fdde9ec62b
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Initiliaze funcion back to 1 (in the toggle registers). Still not working
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2026-04-06 17:39:05 -03:00 |
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canisio
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84b795203a
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pulse generator integrated but not working
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2026-04-06 16:16:42 -03:00 |
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canisio
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ada7e324cd
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Fixed register address on "update parameters"
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2026-04-06 15:15:55 -03:00 |
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canisio
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7813d9744c
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Modified PS part and interface towards pulse generation integration
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2026-04-06 12:26:06 -03:00 |
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canisio
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05b74503dc
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Fixed init callback for pulse gen testbench
v1.0
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2026-04-06 10:45:21 -03:00 |
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canisio
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72b9a34db9
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Ready to move from sine to pulse generator (Tx Subsystem)
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2026-04-06 10:23:23 -03:00 |
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canisio
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3c6ae0cfe9
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finished organization of init funcions and parameters
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2026-04-04 16:05:17 -03:00 |
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canisio
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eb14676581
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Oganize preload and init functions and parameters (ongoing)
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2026-04-04 15:16:58 -03:00 |
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canisio
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040834d511
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added docs folder to project path.
tested remotely. OK
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2026-04-03 20:47:13 -03:00 |
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canisio
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a92709b500
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Added bypass of channelizer to the documentation
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2026-04-02 17:39:01 -03:00 |
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canisio
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27ec12161c
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detailed subsystems
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2026-04-02 17:36:23 -03:00 |
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canisio
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5caaa7fd9a
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updated README
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2026-04-02 17:32:03 -03:00 |
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canisio
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ea0ecefae1
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Added documentation and updated README
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2026-04-02 17:29:24 -03:00 |
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canisio
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e810145620
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Pulse Generator TB validated
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2026-04-02 17:08:44 -03:00 |
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canisio
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a82aed0d5a
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Changed NCO to complex on TBm_chirp
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2026-04-02 16:43:03 -03:00 |
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canisio
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62ab58b741
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Changed Update parameter subsystem on chirp TB to pulse fc and pulse BW.
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2026-04-02 16:28:41 -03:00 |
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canisio
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8e397fa41e
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Added draft to TBm_chirp model. Added init function script to testbench
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2026-04-02 12:03:59 -03:00 |
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canisio
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790c2fdb37
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added placeholder for chirp block
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2026-04-01 12:05:57 -03:00 |
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canisio
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872fbfcd6e
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Minor changes
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2026-04-01 11:51:59 -03:00 |
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canisio
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9794b2d540
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tested on HW. Bypass ok.
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2026-03-31 18:47:13 -03:00 |
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canisio
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b72a8cd616
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added time scope to interface
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2026-03-31 18:00:27 -03:00 |
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canisio
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f66c3ffd06
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Changed interface model to reflect bypass
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2026-03-31 17:51:26 -03:00 |
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canisio
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0c6938bff2
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commented initialize register on proc model
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2026-03-31 17:25:01 -03:00 |
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canisio
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66ad6149e6
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Added switch and led (physical)
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2026-03-31 16:41:27 -03:00 |
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canisio
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a9b4ad9e17
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Added bypass toggle via memory mapped register
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2026-03-31 16:17:34 -03:00 |
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canisio
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0ea6881d1e
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Added bypass to Rx on FPGA. Test OK
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2026-03-31 15:55:46 -03:00 |
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canisio
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278e318715
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Added simulink model to testbench bypass funcion (bypass folder)
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2026-03-31 14:26:45 -03:00 |
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canisio
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e0765a6afe
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Added bypass funcion and its testbench (bypass folder)
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2026-03-31 14:25:43 -03:00 |
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canisio
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dd70d58f2a
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Added frtt_codegen folder to the project initialization
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2026-03-31 09:19:28 -03:00 |
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canisio
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d8a9e026ff
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Added testbench for simulink model. Added f0 option to both testbenches
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2026-03-30 16:01:46 -03:00 |
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canisio
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1613ae8ad9
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Ran codegen for mex and tested. Working ok
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2026-03-30 11:44:31 -03:00 |
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canisio
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7b04d52204
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Added frft functions towards codegen (c code on PS)
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2026-03-30 11:16:12 -03:00 |
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canisio
|
30b31509c1
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Updated README
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2026-03-30 09:30:16 -03:00 |
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canisio
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10644b0475
|
added README
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2026-03-27 18:41:29 -03:00 |
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canisio
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43f91b281b
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Tested on board. Running ok. Updated interface model and added shortcut to it.
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2026-03-27 17:52:13 -03:00 |
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canisio
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89ecf79e61
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Added comment os PS system. Info from training says the time-driven tasks are all inside the processor block, except the event driven and the initialize
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2026-03-27 17:17:28 -03:00 |
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canisio
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13263f4f33
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Removed one of the channels and respective beamforming on Tx and Rx. Simulation ok. Kept the read registers of the angles as placeholders for future use.
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2026-03-27 16:51:41 -03:00 |
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canisio
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81ca3ee48c
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Added renamed prj file
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2026-03-27 15:52:18 -03:00 |
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canisio
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2e297e7f07
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Rename project and clean tracked files
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2026-03-27 15:51:00 -03:00 |
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canisio
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7c361a9608
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Prepare to remove one of the channels. The idea is to transform the beamforming project in a simple wideband detector.
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2026-03-27 13:24:50 -03:00 |
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canisio
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584db6233c
|
- Added utilities for frequency planning
- Changed freq plane to: Fs 4096, int/dec 8X, Mixers 768
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2026-03-27 12:50:10 -03:00 |
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canisio
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d5bbdfb435
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Changed NCO on AD/DA to 0Hz. Changed language for HDL IP to Verilog. Cleaned up for new soc_prj generation
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2026-03-25 18:23:42 -03:00 |
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canisio
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89c8003f5a
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Added sw interface model (controls hardware running on board).
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2026-03-25 17:21:09 -03:00 |
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canisio
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7c1292ae5c
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Added startup function to project (setup HDL tool on it)
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2026-03-25 16:15:16 -03:00 |
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canisio
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c86497656b
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Changed fs to 1024MSPS and added double-sided spectrum visualization. FFT Shifit with two selectors and one concatenate
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2026-03-24 18:10:26 -03:00 |
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canisio
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ac2e7bcece
|
Initial
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2026-03-24 12:44:45 -03:00 |
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