docs: update documentation for capture redesign and validation

changed pulseWidth to pulseT.

README.md

@@ -0,0 +1,92 @@
+# 📡 RFSoC Channelizer + PS Processing (R-ESM Prototype)
+
+## Overview
+
+This project is based on the RFSoC SoC Blockset reference design, adapted as a prototype for a Radar Electronic Support Measures (R-ESM) receiver.
+
+The system implements a high-throughput signal chain in the FPGA (PL) and performs frame-based processing in the processor (PS).
+
+---
+
+## Current Status
+
+- Tx subsystem: LFM pulse generator (DDS-based, complex output)
+- Rx subsystem: fully functional channelizer pipeline (PFB-based) or bypass
+- PL → PS interface: AXI4-Stream + DMA operational
+- PS processing: frame-based algorithm on a Data Process Window (DPW)
+
+---
+
+## System Architecture
+
+Tx (PL)  
+→ Waveform Generator (LFM / CW / Pulsed)  
+→ DAC  
+→ RF Loopback / Input  
+
+Rx (PL)   
+→ ADC  
+→ Channelizer (PFB, 512 bins) / Bypass / Counter  
+→ Capture (frame control)  
+→ AXI4-Stream (128-bit, 4 samples/clock)  
+→ DMA (S2MM)  
+→ PS Memory  
+→ Processor Algorithm
+
+Post Processing (PS)  
+→ Triggered Capture  
+→ Sample Unpacking (I/Q)  
+→ Data Reshaping → [FrameSize x nFrames x nTriggers]  
+→ Host Communication / Processing / Visualization
+→ One DPW is a windows of FrameSize x nFrames samples
+
+---
+
+## Key Parameters
+
+- ADC Sampling Rate: 4096 MSPS  
+- Decimation: 8  
+- Effective BW: 512 MHz  
+- Channels (FFT size): 512  
+- Samples per clock: 4  
+- FPGA clock: 128 MHz  
+- Frame size (PS): 512 samples  
+
+---
+
+## 📚 Documentation
+
+### FPGA (PL)
+
+- [Tx Subsystem (Pulse Generator)](docs/pl_tx_subsystem.md)
+- [Rx Subsystem (Channelizer)](docs/pl_rx_subsystem.md)
+
+### Processor (PS)
+
+- [PS Subsystem](docs/ps_subsystem.md)
+
+---
+
+## System Flow
+
+Tx → Rx → PS
+
+- Tx generates waveform  
+- Rx captures and channelizes  
+- PS processes frames  
+
+---
+
+## Roadmap
+
+1. Functional FrFT (PS)
+2. Profiling
+3. NEON optimization
+4. Throughput tuning
+5. PL acceleration
+
+---
+
+## Key Takeaway
+
+First make it work end-to-end, then make it fast.

codegen_frft/TBc_lfm_fracF.m

@@ -0,0 +1,142 @@
+%% FrFT Validation Script (Reference vs Original)
+% Author: Canisio Barth
+
+clear; clc; close all;
+
+%% Parameters
+Fs = 512e6;          % Sampling rate
+T  = 1e-6;           % Signal duration
+N  = Fs*T;           % 512 samples
+
+n = (0:N-1).';
+t = (n - N/2)/ Fs;
+
+% Beta range (Hz/s)
+betas = (-32e12 : 8e12 : 32e12);
+
+% Order sweep (for heatmap)
+a_vec = linspace( 0.5,  1.5, 100);
+
+% Center frequency 
+f0 = 0e6;   % center frequency (Hz) — set as needed
+
+%% ============================================================
+%% A) HEATMAP (single chirp, order sweep)
+%% ============================================================
+
+beta0 = 64e12; % pick one chirp for visualization
+
+% Generate LFM chirp
+x = exp(1j*(2*pi*f0*t + pi*beta0*t.^2));
+
+% External interpolation (IMPORTANT)
+x_interp = bizinter(x);
+
+N_interp = length(x_interp);
+N_out = N_interp/2; % after decimation
+
+% Allocate
+FrFT_map_ref = zeros(N_out, length(a_vec));
+FrFT_map_cmp = zeros(N_out, length(a_vec));
+
+for k = 1:length(a_vec)
+    a = a_vec(k);
+
+    % Reference
+    y_ref = fracF_ref(x_interp, a);
+    %y_ref = fracF_cg(x_interp, a);
+
+    % Comparison (original / other implementation)
+    %y_cmp = fracF_cg(x_interp, a);
+    y_cmp = fracF_cg_mex(single(x_interp), single(a));
+
+    FrFT_map_ref(:,k) = y_ref;
+    FrFT_map_cmp(:,k) = double(y_cmp);
+end
+
+% Global relative error
+rel_err_global = norm(FrFT_map_ref(:) - FrFT_map_cmp(:)) / ...
+                 norm(FrFT_map_ref(:));
+
+fprintf('Global relative error: %.3e\n', rel_err_global);
+
+% Plot - Reference
+figure;
+imagesc(a_vec, -N_out/2:N_out/2-1, abs(FrFT_map_ref) / sqrt(N));
+axis xy;
+xlabel('Order a');
+ylabel('Index');
+title('FrFT Magnitude (Reference)');
+colorbar;
+
+% Plot - Comparison
+figure;
+imagesc(a_vec, -N_out/2:N_out/2-1, abs(FrFT_map_cmp) / sqrt(N));
+axis xy;
+xlabel('Order a');
+ylabel('Index');
+title('FrFT Magnitude (Comparison)');
+colorbar;
+
+% Plot - Difference
+figure;
+rel_err_map = abs(FrFT_map_ref - FrFT_map_cmp) ./ ...
+              (abs(FrFT_map_ref) + eps);
+
+imagesc(a_vec, -N_out/2:N_out/2-1, rel_err_map);
+axis xy;
+xlabel('Order a');
+ylabel('Index');
+title('Absolute Difference |Ref - Cmp|');
+colorbar;
+
+
+%% ============================================================
+%% B) PEAK VS BETA (matched order)
+%% ============================================================
+
+peak_ref = zeros(size(betas));
+peak_cmp = zeros(size(betas));
+
+for i = 1:length(betas)
+    beta = betas(i);
+
+    % Generate chirp
+    x = exp(1j*(2*pi*f0*t + pi*beta*t.^2));
+
+    % External interpolation
+    x_interp = bizinter(x);
+
+    % Matched order
+    a = -(2/pi)*atan(Fs/(beta*T));
+
+    % Compute FrFT
+    y_ref = fracF_ref(x_interp, a);
+    %y_ref = fracF_cg(x_interp, a);
+    
+    %y_cmp = fracF_cg(x_interp, a);
+    y_cmp = fracF_cg_mex(single(x_interp), single(a));
+
+    % Normalized peak magnitude
+    peak_ref(i) = max(abs(y_ref)) / sqrt(N);
+    peak_cmp(i) = max(abs(y_cmp)) / sqrt(N);
+end
+
+% Plot peaks
+figure;
+plot(betas/1e12, peak_ref, 'o-', 'LineWidth', 1.5); hold on;
+plot(betas/1e12, peak_cmp, 's--', 'LineWidth', 1.5);
+xlabel('\beta (MHz/\mus)');
+ylabel('Peak Magnitude');
+title('Peak vs Chirp Rate');
+legend('Reference','Comparison');
+grid on;
+
+% Plot relative error
+figure;
+rel_err = abs(peak_ref - peak_cmp) ./ peak_ref;
+plot(betas/1e12, rel_err, 'o-', 'LineWidth', 1.5);
+xlabel('\beta (MHz/\mus)');
+ylabel('Relative Error');
+title('Relative Error between Implementations');
+grid on;

codegen_frft/bizinter.m

@@ -0,0 +1,37 @@
+function xint=bizinter(x)
+
+N=length(x);
+im = 0;
+if sum(abs(imag(x)))>0
+  im = 1;
+  imx = imag(x);
+  x  = real(x);
+end
+
+x2=x(:);
+x2=[x2.'; zeros(1,N)];
+x2=x2(:);
+xf=fft(x2);
+if rem(N,2)==1      %N = odd
+	N1=fix(N/2+1); N2=2*N-fix(N/2)+1;
+	xint=2*real(ifft([xf(1:N1); zeros(N,1)  ;xf(N2:2*N)].'));
+else
+	xint=2*real(ifft([xf(1:N/2); zeros(N,1)  ;xf(2*N-N/2+1:2*N)].'));
+end
+if ( im == 1)
+ x2=imx(:);
+ x2=[x2.'; zeros(1,N)];
+ x2=x2(:);
+ xf=fft(x2);
+ if rem(N,2)==1      %N = odd
+	N1=fix(N/2+1); N2=2*N-fix(N/2)+1;
+	xmint=2*real(ifft([xf(1:N1); zeros(N,1)  ;xf(N2:2*N)].'));
+ else
+	xmint=2*real(ifft([xf(1:N/2); zeros(N,1)  ;xf(2*N-N/2+1:2*N)].'));
+ end
+ xint = xint + 1j*xmint;
+end
+
+xint = xint(:);
+
+end

codegen_frft/fracF_cg.m

@@ -0,0 +1,80 @@
+function F = fracF_cg(f, a)
+%#codegen
+%% fracF_cg Fractional Fourier Transform (FrFT) - codegen-ready version
+%
+%   Author: Canisio Barth
+%
+%   F = fracF_cg(f, a) computes the Fractional Fourier Transform (FrFT)
+%   of the input signal 'f' for a single transform order 'a'.
+%
+%   This version is adapted for MATLAB Coder and hardware-oriented workflows.
+%
+%   Key characteristics:
+%       - Fixed input size: [1024 x 1] complex(single)
+%       - Output size: [512 x 1] complex(single)
+%       - Assumes input 'f' is already interpolated externally
+%       - No input validation (assumes valid scalar 'a' in core region)
+%       - Deterministic execution (no branching, no dynamic allocation)
+%
+%   INPUTS:
+%       f   - [1024 x 1] complex(single)
+%       a   - scalar single
+%
+%   OUTPUTS:
+%       F   - [512 x 1] complex(single)
+%
+%   Notes:
+%       - Internal FFT size = 2048
+%       - Designed for code generation and future FPGA mapping
+
+% Fixed sizes
+N    = 1024;
+%N2   = 512;
+Nfft = 2048;
+
+% Ensure types
+pi_s = single(pi);
+
+% Transform parameter
+phi = a * (pi_s / 2);
+
+% Precompute trig terms
+tan_half_phi = tan(phi / 2);
+sin_phi = sin(phi);
+cos_phi = cos(phi);
+
+csc_phi = 1 / sin_phi;
+cot_phi = cos_phi / sin_phi;
+
+twoDelta = 2 * sqrt(single(N) / 2);
+
+%% === Chirp A ===
+n = single((-N/2:N/2-1).') / twoDelta;
+
+Achirp = exp(-1j * pi_s * (n .* n) * tan_half_phi);
+
+%% Chirp multiplication #1
+g = Achirp .* f;
+
+%% === Chirp B ===
+m = single((-N:N-1).') / twoDelta;
+
+Bchirp = exp(1j * pi_s * csc_phi .* (m .* m));
+
+%% === Zero-padded buffer ===
+g_pad = complex(zeros(Nfft,1,'single'));
+g_pad(1:N) = g;
+
+%% === FFT convolution ===
+G = ifft( fft(g_pad) .* fft(Bchirp) );
+
+%% Extract valid part and decimate
+G_valid = G(N+1:2:end);   % [512 x 1]
+
+%% Complex phase constant
+Aphi = sqrt(1 - 1j * cot_phi);
+
+%% === Chirp multiplication #2 ===
+F = (Aphi / twoDelta) .* G_valid .* Achirp(1:2:end);
+
+end

codegen_frft/fracF_ref.m

@@ -0,0 +1,77 @@
+function [F] = fracF_ref(f, a)
+%% fracF_ref Reference Fractional Fourier Transform (FrFT) implementation
+%
+%   Author: Canisio Barth
+%
+%   F = fracF_ref(f, a) computes the Fractional Fourier Transform (FrFT)
+%   of the input signal 'f' for a single transform order 'a'.
+%
+%   This function serves as a reference (golden model) for validation and
+%   comparison against future code generation and hardware-oriented
+%   implementations.
+%
+%   Key characteristics:
+%       - Scalar transform order 'a' (no vector support).
+%       - Assumes input signal 'f' is already interpolated externally.
+%       - Maintains original algorithm structure, including internal
+%         decimation after convolution.
+%       - Uses full MATLAB flexibility (not yet restricted for codegen).
+%
+%   INPUTS:
+%       f   - Input signal, [N x 1] column vector.
+%             IMPORTANT: 'f' must already be interpolated (expanded signal).
+%
+%       a   - Scalar transform order.
+%             Expected to satisfy: 0.5 < |a| < 1.5
+%
+%   OUTPUTS:
+%       F   - Fractional Fourier Transform, [(N/2) x 1] column vector.
+%             (Decimated output, consistent with original algorithm.)
+%
+%   LIMITATIONS:
+%       - No internal interpolation is performed.
+%       - Only valid for scalar 'a'.
+%       - Assumes caller enforces correct parameter range and signal format.
+%
+%   See also: fracF (Ozaktas)
+
+% Validate scalar 'a'
+if ~isscalar(a)
+    error('Parameter ''a'' must be scalar.');
+end
+
+% Range check (core region)
+if abs(a) < 0.5 || abs(a) > 1.5
+    error('Parameter ''a'' must be within the interval [0.5, 1.5].');
+end
+
+N = length(f); % already interpolated length
+
+% Transform parameter
+twoDelta = 2 * sqrt(N/2);
+phi = a * pi / 2;
+
+% === Chirp A ===
+n = ((-N/2:N/2-1) / twoDelta).';
+Achirp = exp(-1j * pi * (n .* n) * tan(phi/2));
+
+% Chirp multiplication #1
+g = Achirp .* f;
+
+% === Chirp B ===
+m = ((-N:N-1) / twoDelta).';
+Bchirp = exp(1j * pi * csc(phi) .* (m .* m));
+
+% === Chirp convolution ===
+G = ifft(fft([g; zeros(N,1)]) .* fft(Bchirp));
+
+% Extract valid part and decimate
+G = G(end/2+1:2:end);
+
+% Complex phase constant
+Aphi = sqrt(1 - 1j * cot(phi));
+
+% === Chirp multiplication #2 ===
+F = (Aphi / twoDelta) .* G .* Achirp(1:2:end);
+
+end

docs/pl_rx_subsystem.md

@@ -0,0 +1,144 @@
+# 📡 PL Rx Subsystem (Channelizer)
+
+[🏠 Project Home](../README.md)
+
+---
+
+## Overview
+
+The Rx subsystem implements a **polyphase filter bank (PFB) channelizer** followed by FFT processing, a **bypass path**, and a **multi-frame capture pipeline**.
+
+It converts wideband ADC input into frequency-domain channels (or raw samples via bypass) and streams the result to the PS.
+
+---
+
+## Architecture
+
+### Channelizer Path (default)
+
+ADC  
+ ↓  
+PFB Channelizer (Decimation + Filtering)  
+ ↓  
+FFT (512 bins)  
+ ↓  
+Capture (frame control)  
+ ↓  
+AXI4-Stream (128-bit, 4 samples/clock)  
+ ↓  
+DMA
+
+---
+
+### Bypass Path (Debug / Raw Data)
+
+ADC  
+ ↓  
+Bypass Path  
+ ↓  
+Capture (frame control)  
+ ↓  
+AXI4-Stream (128-bit, 4 samples/clock)  
+ ↓  
+DMA
+
+---
+
+## Capture Pipeline
+
+- Multi-frame acquisition (configurable nFrames)
+- Frame size: 512 samples
+- Supports asynchronous capture start (not frame-aligned)
+- TLAST asserted at frame boundaries
+
+### Behavior
+
+- First frame may be partial
+- Frames may contain ≤ 2 frame indices (expected)
+- DPW spans nFrames frames but covers nFrames + 1 frame regions
+
+---
+
+## Processing Chain (Channelizer Mode)
+
+### ADC Input
+- Sampling rate: 4096 MSPS
+- Data type: **fixdt(1,16,15)** (Q1.15)
+
+### PFB Channelizer
+- Decimation: 8
+- Effective bandwidth: 512 MHz
+
+### FFT
+- Size: 512
+- Produces frequency bins
+
+### Capture
+- Defines frame boundaries (512 samples)
+- Generates TLAST
+
+---
+
+## Numeric Format and Scaling
+
+### System Standardization
+
+- End-to-end Q1.15 (**fixdt(1,16,15)**)
+
+### Channelizer Output Scaling
+
+- Native: **sFix25_En23**
+- Quantized to: **fixdt(1,16,15)** (round + saturate)
+
+---
+
+## Data Packing (Updated)
+
+- 4 samples per clock
+- Each sample: complex (16-bit real + 16-bit imag)
+- Packed into **128-bit AXI4-Stream word**
+
+Benefits:
+- Matches datapath parallelism
+- Efficient DMA transfers
+- Eliminates need for serializer stage
+
+---
+
+## AXI4-Stream Output
+
+- Width: 128 bits
+- Contains 4 complex samples per cycle
+- TLAST = frame boundary
+
+---
+
+## Debug / Validation Features
+
+A counter-based debug mode is implemented:
+
+- Real part → sample counter (0..511)
+- Imag part → frame index
+
+Used to validate:
+- Sample continuity
+- Frame boundaries
+- DMA ordering and integrity
+
+---
+
+## Key Characteristics
+
+- Fully streaming pipeline
+- Deterministic latency
+- High throughput (4 samples/clock)
+- Dual-mode operation (channelizer / bypass)
+- Validated up to nFrames = 1024
+
+---
+
+## 🔗 Related Components
+
+- [🏠 Project Home](../README.md)
+- [PL Tx Subsystem](pl_tx_subsystem.md)
+- [PS Subsystem](ps_subsystem.md)

docs/pl_tx_subsystem.md

@@ -0,0 +1,177 @@
+# 📡 PL Tx Subsystem (Pulse & Continuous LFM Generator)
+
+[🏠 Project Home](../README.md)
+
+---
+
+## Overview
+
+The Tx subsystem implements a **pulse-based and continuous Linear Frequency Modulated (LFM) chirp generator** using a DDS/NCO architecture in the FPGA (PL).
+
+The generator produces **complex baseband output**:
+
+x[n] = exp(j·φ[n])
+
+and operates deterministically in the PL after a trigger from the PS.
+
+---
+
+## Architecture
+
+TxPulseStart (PS)
+        ↓
+pulse_gen_ctrl (FSM)
+        ↓
+   tx_active
+        ↓
+Phase Increment Logic
+        ↓
+      NCO (DDS)
+        ↓
+   Complex Output (I/Q)
+
+---
+
+## Operating Modes
+
+The subsystem now supports multiple Tx modes:
+
+### 1. Pulsed LFM (default)
+
+- Chirp generated only during pulse window
+- Phase resets at each pulse start
+- Standard radar burst operation
+
+---
+
+### 2. CW Mode (Continuous Wave)
+
+- `tx_active = 1` continuously
+- Generates a single-tone output
+- Achieved by setting constant phase increment
+
+---
+
+### 3. Continuous LFM (Workaround Implementation)
+
+- `tx_active` forced HIGH continuously  
+- A **1-cycle LOW pulse** is inserted periodically  
+- This LOW→HIGH transition **resets the NCO**
+
+Result:
+- Continuous chirp
+- Bounded bandwidth
+- Periodic repetition of LFM
+
+---
+
+## Chirp Generation Principle
+
+The chirp is generated using a second-order phase accumulator:
+
+Δφ[n] = Δφ[n−1] + step  
+φ[n]  = φ[n−1] + Δφ[n]
+
+This results in a linear frequency sweep.
+
+---
+
+## Parameterization (PS → PL)
+
+Inputs:
+
+- Center frequency: Fc  
+- Bandwidth: B  
+- Pulse width: N (samples)
+
+Derived internally:
+
+f_start = Fc − B/2  
+step    = B / (N − 1)
+
+These values are converted to DDS phase increments before being written to PL registers.
+
+---
+
+## Pulse Timing (FSM)
+
+States:
+
+- IDLE: waits for trigger and latches parameters  
+- ACTIVE: generates pulses  
+- DONE: waits for trigger reset  
+
+---
+
+## Timing Behavior
+
+### Pulsed Mode
+
+|<------ PRI ------>|
+|<-- pulse -->| idle |
+
+- tx_active = 1 → chirp output  
+- tx_active = 0 → output zero  
+
+---
+
+### Continuous LFM Mode
+
+tx_active behavior:
+
+1 1 1 1 1 0 1 1 1 1 ...
+
+- 1-cycle LOW inserted at end of chirp period  
+- Rising edge resets NCO  
+- Defines chirp repetition interval  
+
+---
+
+## CW / Continuous LFM Implementation Details
+
+- CW mode bypasses FSM output
+- A dedicated counter generates periodic reset pulses
+- Reset timing is based on `pulse_width_cycles`
+
+Important:
+
+- Reset pulse is exactly **1 clock cycle**
+- Ensures deterministic NCO restart
+- Decoupled from PRI/FSM timing
+
+---
+
+## Burst Trigger (PS Interaction)
+
+- Controlled via TxPulseStart (memory-mapped register)
+- Rising edge triggers burst
+- PL runs autonomously afterward
+
+---
+
+## Key Characteristics
+
+- Deterministic timing (128 MHz)
+- Efficient DDS (adder-based)
+- Complex output (I/Q)
+- Supports:
+  - Pulsed radar mode
+  - Continuous wave (CW)
+  - Continuous LFM (periodic chirp)
+
+---
+
+## Design Notes
+
+- FSM controls **timing (when to transmit)**
+- NCO controls **frequency evolution**
+- Continuous LFM implemented via **tx_active edge reuse**
+- Minimal hardware overhead (no additional NCO logic)
+
+---
+
+## 🔗 Related Components
+
+- [🏠 Project Home](../README.md)
+- [PL Rx Subsystem](pl_rx_subsystem.md)
+- [PS Subsystem](ps_subsystem.md)

docs/ps_subsystem.md

@@ -0,0 +1,140 @@
+# 🧠 PS Subsystem (Control + Capture + Processing)
+
+[🏠 Project Home](../README.md)
+
+---
+
+## Overview
+
+The PS subsystem is responsible for:
+
+- System initialization
+- Configuring PL subsystems
+- Triggering captures
+- Receiving data via DMA
+- Preparing data for processing and visualization
+
+The current implementation acts as a **placeholder for post-processing**, focusing on reliable data acquisition and host interaction.
+
+---
+
+## Responsibilities
+
+### Control & Initialization
+
+- Configure PL parameters:
+  - Tx waveform configuration
+  - Capture parameters (nFrames, etc.)
+- Initialize DMA and memory buffers
+- Manage system startup
+
+---
+
+### Trigger & Capture
+
+- Generates capture trigger (software-controlled)
+- Controls DPW acquisition timing
+- Each trigger initiates one DPW capture
+
+---
+
+### DMA Handling
+
+- AXI4-Stream → DMA (S2MM)
+- Receives **128-bit stream** (4 samples per clock)
+- Stores data in PS DDR memory
+
+Configuration:
+- Frame size: 512 samples
+- nFrames: configurable (validated up to 1024)
+
+---
+
+## Data Format
+
+### Raw DMA Data
+
+- Packed complex samples
+- 16-bit real + 16-bit imag per sample
+- 4 samples per 128-bit word
+
+---
+
+### Processing Representation
+
+Data is unpacked and reshaped into:
+
+```
+[FrameSize x nFrames x nTriggers]
+```
+
+---
+
+## Processing Pipeline (Current)
+
+DMA  
+→ Unpack samples (I/Q separation)  
+→ Convert to complex representation  
+→ Reshape into 3D structure  
+→ Visualization / basic analysis  
+
+---
+
+## Validation Support
+
+Uses counter-based validation:
+
+- Real part → sample counter
+- Imag part → frame index
+
+Enables verification of:
+
+- Data continuity
+- Frame alignment
+- Correct ordering from DMA
+
+---
+
+## Execution Model
+
+- Triggered (event-based)
+- Burst capture (DPW)
+- Not continuous real-time streaming
+
+---
+
+## Performance Notes
+
+- Designed for correctness and validation (not optimized)
+- Bottleneck: unpacking + data movement
+- Full-rate continuous processing not supported
+
+---
+
+## Role in System
+
+The PS currently serves as:
+
+- Control interface
+- Data acquisition manager
+- Pre-processing stage
+
+Future implementations will replace the current processing with advanced algorithms (e.g., FrFT).
+
+---
+
+## Future Work
+
+- FrFT-based processing
+- Timestamp integration
+- UDP streaming
+- Optimization (NEON / vectorization)
+- Metadata extraction (move complexity to PL)
+
+---
+
+## 🔗 Related Components
+
+- [🏠 Project Home](../README.md)
+- [PL Tx Subsystem](pl_tx_subsystem.md)
+- [PL Rx Subsystem](pl_rx_subsystem.md)

resources/project/Abllu374wtDd3IliE-5ZoGpf8mM/O_Wj2lFHsFw-dAu1iDbjtB-rERUd.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info/>

resources/project/Abllu374wtDd3IliE-5ZoGpf8mM/O_Wj2lFHsFw-dAu1iDbjtB-rERUp.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="aux" type="File"/>

resources/project/Abllu374wtDd3IliE-5ZoGpf8mM/TelF4YKeHIop9sma5ly27aHFycIp.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="soc_rfsoc_prj_startup.m" type="File"/>

resources/project/Abllu374wtDd3IliE-5ZoGpf8mM/a4IuKwbTrz65HsB1qy2BUvphPvUp.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="soc_rfsoc_preload.m" type="File"/>

resources/project/Abllu374wtDd3IliE-5ZoGpf8mM/d5dEC3kotuZeerJ4IRjJh3LU3nMd.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info/>

resources/project/Abllu374wtDd3IliE-5ZoGpf8mM/d5dEC3kotuZeerJ4IRjJh3LU3nMp.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="post_processing" type="File"/>

resources/project/Abllu374wtDd3IliE-5ZoGpf8mM/ep2eC_pbgpB45JNIfZ_kN-IOldEp.xml

@@ -1,2 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<Info location="soc_rfsoc_startup.m" type="File"/>

resources/project/Abllu374wtDd3IliE-5ZoGpf8mM/iQaSRrC-noYsKgVFmEoWEQpEbbMp.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="soc_rfsoc_postload.m" type="File"/>

resources/project/EEtUlUb-dLAdf0KpMVivaUlztwA/-0dX7hmZQsRXWhdykAvakl20lP8d.xml

@@ -1,2 +0,0 @@
-<?xml version='1.0' encoding='UTF-8'?>
-<Info Ref="" Type="Relative"/>

resources/project/EEtUlUb-dLAdf0KpMVivaUlztwA/-0dX7hmZQsRXWhdykAvakl20lP8p.xml

@@ -1,2 +0,0 @@
-<?xml version='1.0' encoding='UTF-8'?>
-<Info location="7ac7702b-30c0-47d0-8a3a-1562b67f2ab5" type="Reference"/>

resources/project/EEtUlUb-dLAdf0KpMVivaUlztwA/LVo7B_RSfnAS3NsdARLSe9kcOFcd.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info Ref="block_pulsegen" Type="Relative"/>

resources/project/EEtUlUb-dLAdf0KpMVivaUlztwA/LVo7B_RSfnAS3NsdARLSe9kcOFcp.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="6a9c972f-52d5-42e0-8c82-940b26905df7" type="Reference"/>

resources/project/EEtUlUb-dLAdf0KpMVivaUlztwA/SwCK9Vqjv5J_5sSeux-jDiWs9yod.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info Ref="block_bypass" Type="Relative"/>

resources/project/EEtUlUb-dLAdf0KpMVivaUlztwA/SwCK9Vqjv5J_5sSeux-jDiWs9yop.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="f7229047-4926-407b-902a-a25e790af1a9" type="Reference"/>

resources/project/EEtUlUb-dLAdf0KpMVivaUlztwA/XNALo81LXKoPpl_sWox0XlMZwrgd.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info Ref="" Type="Relative"/>

resources/project/EEtUlUb-dLAdf0KpMVivaUlztwA/XNALo81LXKoPpl_sWox0XlMZwrgp.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="a92ac691-f104-48a3-8517-c0b00eec410f" type="Reference"/>

resources/project/EEtUlUb-dLAdf0KpMVivaUlztwA/aIKCkzvF2b1sr3-2vSSYXiPFCBcd.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info Ref="utilities/aux" Type="Relative"/>

resources/project/EEtUlUb-dLAdf0KpMVivaUlztwA/aIKCkzvF2b1sr3-2vSSYXiPFCBcp.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="ac65d1bc-e8fa-4056-83e4-eaba335b5aa3" type="Reference"/>

resources/project/EEtUlUb-dLAdf0KpMVivaUlztwA/gRP9wXFdtHX_ypmAn6DejA7dq5gd.xml

@@ -1,2 +1,2 @@
-<?xml version='1.0' encoding='UTF-8'?>
+<?xml version="1.0" encoding="UTF-8"?>
 <Info Ref="referencedmodels" Type="Relative"/>

resources/project/EEtUlUb-dLAdf0KpMVivaUlztwA/gRP9wXFdtHX_ypmAn6DejA7dq5gp.xml

@@ -1,2 +1,2 @@
-<?xml version='1.0' encoding='UTF-8'?>
+<?xml version="1.0" encoding="UTF-8"?>
 <Info location="15258b0d-3597-4917-9d8b-5ec7677aa528" type="Reference"/>

resources/project/EEtUlUb-dLAdf0KpMVivaUlztwA/jZgU_Ahn9qjarKQXLgCdj2YqbVAd.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info Ref="block_capture" Type="Relative"/>

resources/project/EEtUlUb-dLAdf0KpMVivaUlztwA/jZgU_Ahn9qjarKQXLgCdj2YqbVAp.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="c26ab781-2c03-423c-8199-bc6903e4e4f7" type="Reference"/>

resources/project/EEtUlUb-dLAdf0KpMVivaUlztwA/lGeuoQeIdXdMS7FJ_dlOk1UnQ7cd.xml

@@ -1,2 +1,2 @@
-<?xml version='1.0' encoding='UTF-8'?>
+<?xml version="1.0" encoding="UTF-8"?>
 <Info Ref="utilities" Type="Relative"/>

resources/project/EEtUlUb-dLAdf0KpMVivaUlztwA/lGeuoQeIdXdMS7FJ_dlOk1UnQ7cp.xml

@@ -1,2 +1,2 @@
-<?xml version='1.0' encoding='UTF-8'?>
+<?xml version="1.0" encoding="UTF-8"?>
 <Info location="082474f0-d7d9-423c-bb63-dc039b2ad79a" type="Reference"/>

resources/project/EEtUlUb-dLAdf0KpMVivaUlztwA/qJvYjNosE_sBwRwPOaE6gx07mA4d.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info Ref="docs" Type="Relative"/>

resources/project/EEtUlUb-dLAdf0KpMVivaUlztwA/qJvYjNosE_sBwRwPOaE6gx07mA4p.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="de23f5bc-2dc5-4828-b061-5d044a37a018" type="Reference"/>

resources/project/EEtUlUb-dLAdf0KpMVivaUlztwA/sOKZQKY-ifD0QKQdTG4oIEFctdkd.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info Ref="utilities/post_processing" Type="Relative"/>

resources/project/EEtUlUb-dLAdf0KpMVivaUlztwA/sOKZQKY-ifD0QKQdTG4oIEFctdkp.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="5bfc0575-1eef-448a-a3a2-ced40deb5860" type="Reference"/>

resources/project/HoHDHQ_WvHAAKj5aJOrvrg_vpt8/xXlmKuOQ7YT_G1elNhbKQIUqSRMd.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info description="RFSoC Channelizer + PS Processing (R-ESM Prototype)&#10;&#10;This project is based on the RFSoC SoC Blockset reference design, adapted as a prototype for a Radar Electronic Support Measures (R-ESM) receiver.&#10;&#10;The system implements a high-throughput signal chain in the FPGA (PL) and performs frame-based processing in the processor (PS)."/>

resources/project/HoHDHQ_WvHAAKj5aJOrvrg_vpt8/xXlmKuOQ7YT_G1elNhbKQIUqSRMp.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="Information" type="Extension"/>

resources/project/KAXfQgCar2Yb8zOxgvf9hdmLP1E/Fd9H20iNQ049h3heONYKHGeEV4Ud.xml

@@ -1,4 +1,4 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<Info File="utilities/soc_rfsoc_startup.m" GroupUUID="default" Icon="" Name="soc_rfsoc_startup" Type="StartUp" Visible="0">
+<Info File="utilities/soc_rfsoc_prj_startup.m" GroupUUID="default" Icon="" Name="soc_rfsoc_startup" Type="StartUp" Visible="0">
     <Extension Name="StartUpPrev" Value="HEAD"/>
 </Info>

resources/project/LpvpJ1uloVvE37aexyCWfqNpR8E/kWZ7pdVGtMo0COXLW0ugDKc6srMp.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="TBm_pulsegen.slx" type="File"/>

resources/project/LpvpJ1uloVvE37aexyCWfqNpR8E/sDGaF7_ioOTLSFvWYTP4rRdxuOId.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info/>

resources/project/LpvpJ1uloVvE37aexyCWfqNpR8E/sDGaF7_ioOTLSFvWYTP4rRdxuOIp.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="1" type="DIR_SIGNIFIER"/>

resources/project/O_Wj2lFHsFw-dAu1iDbjtB-rERU/UpuFGRcvFtU5S3cyXBcvri-IBWAd.xml

@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info>
+    <Category UUID="FileClassCategory">
+        <Label UUID="design"/>
+    </Category>
+</Info>

resources/project/O_Wj2lFHsFw-dAu1iDbjtB-rERU/lDMgbB2qVwwu-5ETYbC5dxpFwTId.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info/>

resources/project/O_Wj2lFHsFw-dAu1iDbjtB-rERU/lDMgbB2qVwwu-5ETYbC5dxpFwTIp.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="1" type="DIR_SIGNIFIER"/>

resources/project/O_Wj2lFHsFw-dAu1iDbjtB-rERU/r-zk_iIlSRLwzoRAmANarULWdgod.xml

@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info>
+    <Category UUID="FileClassCategory">
+        <Label UUID="design"/>
+    </Category>
+</Info>

resources/project/O_Wj2lFHsFw-dAu1iDbjtB-rERU/xtQ8mZo1_ExmTkcSjfJ0gi-M3Skd.xml

@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info>
+    <Category UUID="FileClassCategory">
+        <Label UUID="design"/>
+    </Category>
+</Info>

resources/project/QuVfFK49N05REJIAYZLQasz_VuM/G0MCWfbLWGDEK-XGehbFPxgX67gd.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info/>

resources/project/QuVfFK49N05REJIAYZLQasz_VuM/G0MCWfbLWGDEK-XGehbFPxgX67gp.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="1" type="DIR_SIGNIFIER"/>

resources/project/QuVfFK49N05REJIAYZLQasz_VuM/Xx0UDP9sUzEZe711HBEUtl4YraYd.xml

@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info>
+    <Category UUID="FileClassCategory">
+        <Label UUID="design"/>
+    </Category>
+</Info>

resources/project/QuVfFK49N05REJIAYZLQasz_VuM/Xx0UDP9sUzEZe711HBEUtl4YraYp.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="TBm_capture.slx" type="File"/>

resources/project/bMFzsIHr-EVKQIO2sqeU-274_I8/6ogmP0ZksmbyaUjs5D-G7nePRvod.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info/>

resources/project/bMFzsIHr-EVKQIO2sqeU-274_I8/6ogmP0ZksmbyaUjs5D-G7nePRvop.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="1" type="DIR_SIGNIFIER"/>

resources/project/bMFzsIHr-EVKQIO2sqeU-274_I8/aye6s7-kaYjVsTGx2onCoqYnyTUd.xml

@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info>
+    <Category UUID="FileClassCategory">
+        <Label UUID="design"/>
+    </Category>
+</Info>

resources/project/bMFzsIHr-EVKQIO2sqeU-274_I8/aye6s7-kaYjVsTGx2onCoqYnyTUp.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="TBm_bypass.slx" type="File"/>

resources/project/d5dEC3kotuZeerJ4IRjJh3LU3nM/F6I45Jz3Y8Cbk8qxkuAN2aHpqcUd.xml

@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info>
+    <Category UUID="FileClassCategory">
+        <Label UUID="design"/>
+    </Category>
+</Info>

resources/project/d5dEC3kotuZeerJ4IRjJh3LU3nM/F6I45Jz3Y8Cbk8qxkuAN2aHpqcUp.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="checkTimeSamples.m" type="File"/>

resources/project/d5dEC3kotuZeerJ4IRjJh3LU3nM/Sqf9uvnGiYyl02crmP5dcX378Bsd.xml

@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info>
+    <Category UUID="FileClassCategory">
+        <Label UUID="design"/>
+    </Category>
+</Info>

resources/project/d5dEC3kotuZeerJ4IRjJh3LU3nM/Sqf9uvnGiYyl02crmP5dcX378Bsp.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="checkFreqSamples.m" type="File"/>

resources/project/d5dEC3kotuZeerJ4IRjJh3LU3nM/YcrfchWz89iaifBeF9RcdywvjvAd.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info/>

resources/project/d5dEC3kotuZeerJ4IRjJh3LU3nM/YcrfchWz89iaifBeF9RcdywvjvAp.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="1" type="DIR_SIGNIFIER"/>

resources/project/d5dEC3kotuZeerJ4IRjJh3LU3nM/jCxeCZZX-Z1DLQ1xfH3hIxhR958d.xml

@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info>
+    <Category UUID="FileClassCategory">
+        <Label UUID="design"/>
+    </Category>
+</Info>

resources/project/d5dEC3kotuZeerJ4IRjJh3LU3nM/jCxeCZZX-Z1DLQ1xfH3hIxhR958p.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="checkCounterSamples.m" type="File"/>

resources/project/qaw0eS1zuuY1ar9TdPn1GMfrjbQ/LpvpJ1uloVvE37aexyCWfqNpR8Ed.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info/>

resources/project/qaw0eS1zuuY1ar9TdPn1GMfrjbQ/LpvpJ1uloVvE37aexyCWfqNpR8Ep.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="block_pulsegen" type="File"/>

resources/project/qaw0eS1zuuY1ar9TdPn1GMfrjbQ/QMJD9OLFzxcTTbPOoh-ahQ4zTRUd.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info/>

resources/project/qaw0eS1zuuY1ar9TdPn1GMfrjbQ/QMJD9OLFzxcTTbPOoh-ahQ4zTRUp.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="README.md" type="File"/>

resources/project/qaw0eS1zuuY1ar9TdPn1GMfrjbQ/QuVfFK49N05REJIAYZLQasz_VuMd.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info/>

resources/project/qaw0eS1zuuY1ar9TdPn1GMfrjbQ/QuVfFK49N05REJIAYZLQasz_VuMp.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="block_capture" type="File"/>

resources/project/qaw0eS1zuuY1ar9TdPn1GMfrjbQ/bMFzsIHr-EVKQIO2sqeU-274_I8d.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info/>

resources/project/qaw0eS1zuuY1ar9TdPn1GMfrjbQ/bMFzsIHr-EVKQIO2sqeU-274_I8p.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="block_bypass" type="File"/>

resources/project/qaw0eS1zuuY1ar9TdPn1GMfrjbQ/rW25SbP5jRWeIzL7_iMpZrrygYkd.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info/>

resources/project/qaw0eS1zuuY1ar9TdPn1GMfrjbQ/rW25SbP5jRWeIzL7_iMpZrrygYkp.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="docs" type="File"/>

resources/project/rW25SbP5jRWeIzL7_iMpZrrygYk/8i67CMLFhpgTFLAi_RBlc2P1lI0d.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info/>

resources/project/rW25SbP5jRWeIzL7_iMpZrrygYk/8i67CMLFhpgTFLAi_RBlc2P1lI0p.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="ps_subsystem.md" type="File"/>

resources/project/rW25SbP5jRWeIzL7_iMpZrrygYk/XVu9f1ZjVk2AJ99l5f9CAU_dcMEd.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info/>

resources/project/rW25SbP5jRWeIzL7_iMpZrrygYk/XVu9f1ZjVk2AJ99l5f9CAU_dcMEp.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="pl_rx_subsystem.md" type="File"/>

resources/project/rW25SbP5jRWeIzL7_iMpZrrygYk/mT-GHnZui1JHuHyjd1ddvO5o-Tsd.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info/>

resources/project/rW25SbP5jRWeIzL7_iMpZrrygYk/mT-GHnZui1JHuHyjd1ddvO5o-Tsp.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info location="1" type="DIR_SIGNIFIER"/>

resources/project/rW25SbP5jRWeIzL7_iMpZrrygYk/uS1pkYbM9dJDnKGtwfzZHrJKyTYd.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Info/>