canisio
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  • Joined on 2026-03-24
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canisio pushed to feature/capture-redesign at canisio/Zcu111ResmReceiver 2026-04-25 12:58:43 -03:00
canisio pushed to feature/capture-redesign at canisio/Zcu111ResmReceiver 2026-04-25 12:58:28 -03:00
df335aac1e validation: verified capture pipeline in counter bypass, sine bypass, and sine channelizer modes (nFrames=8)
canisio pushed to feature/capture-redesign at canisio/Zcu111ResmReceiver 2026-04-25 11:53:28 -03:00
1ebf8aa076 codegen: increase max identifier length to 64 in soc_rfsoc_proc and gm_soc_rfsoc_top_sw
canisio pushed to feature/capture-redesign at canisio/Zcu111ResmReceiver 2026-04-25 11:29:14 -03:00
f9a2eff397 validate sine over bypass using a post processing script in the logged data. Added folter post_processing and script checkTimeSamples
canisio pushed to feature/capture-redesign at canisio/Zcu111ResmReceiver 2026-04-24 17:31:22 -03:00
2f5a466ace Visualization blocks, rate changed to TsSW/nFrames
canisio pushed to feature/capture-redesign at canisio/Zcu111ResmReceiver 2026-04-24 17:26:17 -03:00
ff3aa5e89f Revert "Created valid_out for conter input test"
canisio pushed to feature/capture-redesign at canisio/Zcu111ResmReceiver 2026-04-24 16:36:19 -03:00
a7e710b603 Created valid_out for conter input test
c10736a5d7 AXI4-S2Software>Main>Advanced>Interconnect: Data width (bits) changed to 128
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canisio pushed to feature/capture-redesign at canisio/Zcu111ResmReceiver 2026-04-24 11:59:19 -03:00
2b7d05b3d9 FPGA Packer: Changed to uint128, changed endianess order of packing (selectors 4,3,2,1)
canisio pushed to feature/capture-redesign at canisio/Zcu111ResmReceiver 2026-04-24 11:33:22 -03:00
4cbe3b5699 renamed array plots os gm model
canisio pushed to feature/capture-redesign at canisio/Zcu111ResmReceiver 2026-04-23 15:26:26 -03:00
bbf87121f0 changed to upper and lower halves after stream read. No difference (only first lane of 4x1 being read)
canisio pushed to feature/capture-redesign at canisio/Zcu111ResmReceiver 2026-04-23 08:53:41 -03:00
525a5f65e5 unchecked "enable sample packing" on signal attributes of AXI4-stream to software
canisio pushed to feature/capture-redesign at canisio/Zcu111ResmReceiver 2026-04-22 16:38:21 -03:00
9a7a05f450 stream read read only first sample of [4 x 1] bundle
canisio pushed to feature/capture-redesign at canisio/Zcu111ResmReceiver 2026-04-22 14:37:33 -03:00
0df1044d13 Input test counter moved to Rx Subsystem
canisio pushed to feature/capture-redesign at canisio/Zcu111ResmReceiver 2026-04-22 12:29:17 -03:00
f5ec4e6b6e sine and channelizer appear to work on board. Need to move counter to Rx to fully validate sample order
canisio pushed to feature/capture-redesign at canisio/Zcu111ResmReceiver 2026-04-22 10:45:12 -03:00
293b0e6c50 Updated memory mapped addresses
canisio pushed to feature/capture-redesign at canisio/Zcu111ResmReceiver 2026-04-22 10:30:18 -03:00
9a0404f1a9 4 dalay on the signals of bypass to align test counter to frame start. Appears to be working. Test on board.
canisio pushed to feature/capture-redesign at canisio/Zcu111ResmReceiver 2026-04-21 18:00:53 -03:00
6098d86851 problem on the bypass sample counter: if delay sof,eof,vali on FSM input ok for counter but wrong for channelizer
canisio pushed to feature/capture-redesign at canisio/Zcu111ResmReceiver 2026-04-21 16:19:57 -03:00
4ad5c3c5ea appear to be working with 4 daley after multi-frame capture. Problem is on visualization,
canisio pushed to feature/capture-redesign at canisio/Zcu111ResmReceiver 2026-04-21 12:25:35 -03:00
4b1b94c424 Added counter mode as input, real part = sample counter, imag part = frame counter. Reset on software trigger
canisio pushed to feature/capture-redesign at canisio/Zcu111ResmReceiver 2026-04-21 10:00:49 -03:00
78a7d1ae68 updated interface model. Still not working