• Joined on 2026-03-24
canisio pushed to feature/capture-redesign at canisio/Zcu111ResmReceiver 2026-04-20 17:11:03 -03:00
97d5494781 updated gm_top_sw. Runs on board, but capture is not in sync
canisio pushed to feature/capture-redesign at canisio/Zcu111ResmReceiver 2026-04-20 17:10:02 -03:00
7f369d8692 runs on the board. But capture is not in sync
canisio pushed to feature/capture-redesign at canisio/Zcu111ResmReceiver 2026-04-20 15:04:18 -03:00
286c464f5a set SoCData as datatype again on the stream read inport (I dont know if this was the problem, but its working again)
canisio pushed to feature/capture-redesign at canisio/Zcu111ResmReceiver 2026-04-20 11:53:31 -03:00
91b02cdc79 organized register... stopped working
canisio pushed to feature/capture-redesign at canisio/Zcu111ResmReceiver 2026-04-20 10:51:12 -03:00
0b1dc081e5 commented display on PS, before testing in the board
canisio pushed to feature/capture-redesign at canisio/Zcu111ResmReceiver 2026-04-20 10:49:25 -03:00
d8fe924f6e tests before trying in the board
canisio pushed to feature/capture-redesign at canisio/Zcu111ResmReceiver 2026-04-17 17:03:39 -03:00
b2ce956f41 Multi-frame capture integrated into full design with trigger-controlled DPW; AXI stream (uint32 [4x1]) and DMA framing aligned; fixed FSM termination condition (no overflow); validated end-to-end (PL→DMA→PS) using counter input for multiple nFrames
canisio pushed to feature/capture-redesign at canisio/Zcu111ResmReceiver 2026-04-17 12:22:16 -03:00
fc50e71ab5 AXI stream updated to uint32 [4x1] format; samples-per-frame aligned to nFrames×512; PS stream read configured accordingly; single-frame (nFrames=1) validated end-to-end (PL→DMA→PS) with correct unpacking and data integrity
canisio pushed to feature/capture-redesign at canisio/Zcu111ResmReceiver 2026-04-17 11:33:21 -03:00
ce87190fba If sw side of AXI4-Stream to Software block is set to fixdt(128), frames appear to be arriving correctly on PS. However, reinterpretation is failing when using option "uint32"
canisio pushed to feature/capture-redesign at canisio/Zcu111ResmReceiver 2026-04-17 08:31:20 -03:00
cb56e78923 changed folder name for all testbench models
canisio pushed to feature/capture-redesign at canisio/Zcu111ResmReceiver 2026-04-16 17:35:13 -03:00
a3d46a9113 New register MF_nFrames added to PS (initialize and data genearation/capture). Not tested
15f20619b1 MultiFrame camputre PL part integrated (no test, no PS)
Compare 2 commits »
canisio pushed to feature/capture-redesign at canisio/Zcu111ResmReceiver 2026-04-16 16:44:49 -03:00
88e9df3dbb Multi-frame capture (trigger-controlled DPW) validated in testbench; added 128-bit packer replacing serializer, correct unpacking (SI reinterpret) and frame reconstruction verified (counter + PFB); implemented VALID gating (zero when idle) and AXI-aligned pipelining; nFrames parameterized in TB
canisio pushed to feature/capture-redesign at canisio/Zcu111ResmReceiver 2026-04-16 11:56:30 -03:00
beb5410390 added visualisation to validate ouput of multiple frames
canisio pushed to feature/capture-redesign at canisio/Zcu111ResmReceiver 2026-04-15 17:52:14 -03:00
2b8f8de030 Validation of multiframe on TBm_capture done.
canisio pushed to feature/capture-redesign at canisio/Zcu111ResmReceiver 2026-04-14 17:57:01 -03:00
9fd110f451 Replace serializer with 128-bit packer and add MultiFrameCapture (testbench)
canisio pushed to feature/capture-redesign at canisio/Zcu111ResmReceiver 2026-04-14 16:46:22 -03:00
aad231b55a AXI with 128 bits and no serializer appears to be working
canisio pushed to feature/capture-redesign at canisio/Zcu111ResmReceiver 2026-04-14 12:25:05 -03:00
3748b65872 implemented sample packer to construct 128 AXI. Partially working (only bypass works?)
canisio pushed to feature/capture-redesign at canisio/Zcu111ResmReceiver 2026-04-14 10:32:06 -03:00
d83006c50c Added counter as input for the TBm_capture
canisio pushed to feature/capture-redesign at canisio/Zcu111ResmReceiver 2026-04-14 09:25:05 -03:00
5e5bba3ce6 Stable 16-bit Q1.15 Rx chain before AXI width upgrade
canisio pushed to feature/capture-redesign at canisio/Zcu111ResmReceiver 2026-04-13 17:47:13 -03:00
ccc6b9cd73 Validate 16-bit Q1.15 Rx chain (baseline, partial validation)