canisio
472dcaf62f
diagram update (added PS)
2026-07-02 15:36:04 -03:00
canisio
29a5afbf7e
updated diagram (PL side ok)
2026-06-26 13:43:42 -03:00
canisio
577a816dbf
updated diagram
2026-06-26 13:41:24 -03:00
canisio
1b56b3c9ca
Updated main readme to show the block diagram
2026-06-26 13:15:55 -03:00
canisio
4accb84e4a
Added block diagram of the system
2026-06-26 13:12:33 -03:00
canisio
a5990ae650
nFrames reduced to 64. Responsiveness is back. So the FrFT implementation is not optimized on the A53 processor. Nevertheless, peak is not concentrated, I still need to figure out parameters of transform and how to cope with this non-ideal case (real life)
2026-06-26 11:34:02 -03:00
canisio
c0b4435cd0
updated documentation (PS)
2026-06-11 13:00:23 -03:00
canisio
2d668be90f
nFrames reduced to 64. Responsiveness is back. So the FrFT implementation is not optimized on the A53 processor. Nevertheless, peak is not concentrated, I still need to figure out parameters of transform and how to cope with this non-ideal case (real life)
2026-06-11 12:43:46 -03:00
canisio
aba2f02820
Test: remove tunnable a
2026-06-11 12:07:30 -03:00
canisio
dd79f8692a
fracF_DPW integrated to external mode. Running very slow
2026-06-11 11:32:17 -03:00
canisio
56d3dd647e
FracF_DPW integrated to design. Not validated yet.
2026-06-10 17:16:58 -03:00
canisio
a37ded1d73
codegen OK!
2026-06-10 16:36:56 -03:00
canisio
7dd20a04fa
compared both TBc and TBm, results are equivalent (not identical because of interpolation filter)
2026-06-10 16:05:30 -03:00
canisio
8f2ae1ec4e
Added a LFM matlab script testbench to validate FrFT DPW
2026-06-10 11:46:16 -03:00
canisio
4f5ac3b5f3
Organized codegen for fracFdpw. Tested with random input in matlab script. OK
2026-06-10 09:59:18 -03:00
canisio
943b582d66
ignore generated files/folders from codegen
2026-06-09 16:28:35 -03:00
canisio
2428f5a861
FrFT DPW processing validade in terms of dimensions and code generation
2026-06-09 16:18:00 -03:00
canisio
f64f4fde31
Added codegen folder and scripts for fracF operating in DPW (matrix)
2026-06-09 16:15:39 -03:00
canisio
22c51e1597
FrFT not working (for each error)
2026-06-09 14:54:59 -03:00
canisio
23a3503cb1
initialization of pulse center freq.
2026-06-09 10:51:09 -03:00
canisio
21c46dc45e
removed subfolders codegen_frft
2026-05-22 15:58:53 -03:00
canisio
99ffaa1bfc
startup funcion adapted to non-vivado machines
2026-05-22 15:42:32 -03:00
canisio
48bbb7102a
first tests on FrFT
2026-05-22 12:57:30 -03:00
canisio
b57260583a
fft of FrFT block changed from FFTW to auto
2026-05-21 17:30:38 -03:00
canisio
8839674480
renamed the scopes to differentiate sim to hw
2026-05-21 17:22:52 -03:00
canisio
005d488d79
Added variant subsystem and placeholder for FrFT. Simulation OK. External gives error
2026-05-19 17:19:30 -03:00
canisio
baedad87fa
NEON optimization enabled for C code generation on both proc and interface models
2026-04-30 17:39:17 -03:00
canisio
19fd4dfb2d
second validation of MeanPowSpec before branch to FrFT. Created slides on interface and tested several combinations of paramters. Resulds within expected.
2026-04-30 12:24:24 -03:00
canisio
1622f922f9
MeanPowSpec validated on board
2026-04-29 17:07:10 -03:00
canisio
041218aa7f
test MeanPowSpec on ZCU111
2026-04-29 16:35:55 -03:00
canisio
d9f7798814
Added Mean Power Spectrum calculation on PS
2026-04-29 16:10:21 -03:00
canisio
1ab873419e
clean version after tagging
2026-04-29 14:11:51 -03:00
canisio
65cef793ac
Removed RMS and Fmax outputs
...
Formatted top diagrams
2026-04-29 11:30:02 -03:00
canisio
99c6b62fc6
Added CwMode as toggle switch
2026-04-29 10:44:14 -03:00
canisio
dc76c69731
added folder "codegen_frft" to the project (it was renamed)
2026-04-29 10:21:17 -03:00
canisio
1d0309f060
Merge branch 'feature/capture-redesign': Integrate capture redesign (multi-frame DMA + validation)
...
- Redesigned capture pipeline for multi-frame acquisition
- Added 128-bit packing and correct endianness handling
- Implemented and validated counter-based integrity checks
- Verified bypass, channelizer, and pulsed signal modes
- Validated scaling up to nFrames=1024 on ZCU111
- Added checkCounterSamples.m for end-to-end validation
This establishes a stable and validated acquisition baseline for
future work (timestamping, UDP streaming, FrFT processing).
2026-04-29 10:15:07 -03:00
canisio
19b0513809
docs: update documentation for capture redesign and validation
2026-04-29 10:03:34 -03:00
canisio
b3ba729f8b
Pulsed input LFM tested on board. Appears ok on both channelizer and bypass.
2026-04-28 17:43:45 -03:00
canisio
c7cb4e770f
Simulated with pulsed signal before testing on ZCU111
2026-04-28 16:31:04 -03:00
canisio
6093942ab3
include check scripts to the project.
...
changed pulseWidth to pulseT.
2026-04-28 15:22:03 -03:00
canisio
edef1dbed3
validation: add checkCounterSamples and verify capture up to 1024 frames on ZCU111
...
Created checkCounterSamples.m to validate sample continuity, counter wraps,
and frame index progression. Verified counter bypass, sine bypass, and
channelizer modes up to nFrames=1024 across 10 DPWs on ZCU111.
2026-04-27 18:32:31 -03:00
canisio
b8d2d6a5dd
updated postload funcion to not break when top is unloaded
2026-04-27 12:21:03 -03:00
canisio
4216288e2a
Removed delays from bypass
...
Removed visualisation from PS
DPW visualization and log outside PS (external mode)
2026-04-27 12:09:46 -03:00
canisio
df335aac1e
validation: verified capture pipeline in counter bypass, sine bypass, and sine channelizer modes (nFrames=8)
...
Validated end-to-end data integrity and visualization across all modes.
2026-04-25 12:58:22 -03:00
canisio
1ebf8aa076
codegen: increase max identifier length to 64 in soc_rfsoc_proc and gm_soc_rfsoc_top_sw
...
Updated Configuration Parameters (Code Generation -> Identifiers) in both
soc_rfsoc_proc and parent model gm_soc_rfsoc_top_sw to set Maximum identifier
length from 31 to 64. This avoids truncation of generated identifiers, reduces
risk of name collisions, and ensures consistency across referenced models to
prevent build mismatches.
2026-04-25 11:53:24 -03:00
canisio
f9a2eff397
validate sine over bypass using a post processing script in the logged data. Added folter post_processing and script checkTimeSamples
2026-04-25 11:28:43 -03:00
canisio
2f5a466ace
Visualization blocks, rate changed to TsSW/nFrames
2026-04-24 17:31:17 -03:00
canisio
ff3aa5e89f
Revert "Created valid_out for conter input test"
...
This reverts commit a7e710b603
2026-04-24 17:25:45 -03:00
canisio
a7e710b603
Created valid_out for conter input test
2026-04-24 16:36:13 -03:00
canisio
c10736a5d7
AXI4-S2Software>Main>Advanced>Interconnect: Data width (bits) changed to 128
2026-04-24 12:14:14 -03:00
