canisio
6093942ab3
include check scripts to the project.
...
changed pulseWidth to pulseT.
2026-04-28 15:22:03 -03:00
canisio
edef1dbed3
validation: add checkCounterSamples and verify capture up to 1024 frames on ZCU111
...
Created checkCounterSamples.m to validate sample continuity, counter wraps,
and frame index progression. Verified counter bypass, sine bypass, and
channelizer modes up to nFrames=1024 across 10 DPWs on ZCU111.
2026-04-27 18:32:31 -03:00
canisio
4216288e2a
Removed delays from bypass
...
Removed visualisation from PS
DPW visualization and log outside PS (external mode)
2026-04-27 12:09:46 -03:00
canisio
df335aac1e
validation: verified capture pipeline in counter bypass, sine bypass, and sine channelizer modes (nFrames=8)
...
Validated end-to-end data integrity and visualization across all modes.
2026-04-25 12:58:22 -03:00
canisio
1ebf8aa076
codegen: increase max identifier length to 64 in soc_rfsoc_proc and gm_soc_rfsoc_top_sw
...
Updated Configuration Parameters (Code Generation -> Identifiers) in both
soc_rfsoc_proc and parent model gm_soc_rfsoc_top_sw to set Maximum identifier
length from 31 to 64. This avoids truncation of generated identifiers, reduces
risk of name collisions, and ensures consistency across referenced models to
prevent build mismatches.
2026-04-25 11:53:24 -03:00
canisio
f9a2eff397
validate sine over bypass using a post processing script in the logged data. Added folter post_processing and script checkTimeSamples
2026-04-25 11:28:43 -03:00
canisio
ff3aa5e89f
Revert "Created valid_out for conter input test"
...
This reverts commit a7e710b603
2026-04-24 17:25:45 -03:00
canisio
a7e710b603
Created valid_out for conter input test
2026-04-24 16:36:13 -03:00
canisio
c10736a5d7
AXI4-S2Software>Main>Advanced>Interconnect: Data width (bits) changed to 128
2026-04-24 12:14:14 -03:00
canisio
2b7d05b3d9
FPGA Packer: Changed to uint128, changed endianess order of packing (selectors 4,3,2,1)
2026-04-24 11:59:16 -03:00
canisio
4cbe3b5699
renamed array plots os gm model
2026-04-24 11:33:15 -03:00
canisio
bbf87121f0
changed to upper and lower halves after stream read. No difference (only first lane of 4x1 being read)
2026-04-23 15:26:22 -03:00
canisio
9a7a05f450
stream read read only first sample of [4 x 1] bundle
2026-04-22 16:38:16 -03:00
canisio
0df1044d13
Input test counter moved to Rx Subsystem
2026-04-22 14:37:28 -03:00
canisio
f5ec4e6b6e
sine and channelizer appear to work on board. Need to move counter to Rx to fully validate sample order
2026-04-22 12:29:13 -03:00
canisio
293b0e6c50
Updated memory mapped addresses
2026-04-22 10:45:07 -03:00
canisio
9a0404f1a9
4 dalay on the signals of bypass to align test counter to frame start. Appears to be working. Test on board.
2026-04-22 10:30:14 -03:00
canisio
6098d86851
problem on the bypass sample counter: if delay sof,eof,vali on FSM input ok for counter but wrong for channelizer
2026-04-21 18:00:44 -03:00
canisio
4ad5c3c5ea
appear to be working with 4 daley after multi-frame capture. Problem is on visualization,
2026-04-21 16:19:43 -03:00
canisio
4b1b94c424
Added counter mode as input, real part = sample counter, imag part = frame counter. Reset on software trigger
2026-04-21 12:25:21 -03:00
canisio
7f369d8692
runs on the board. But capture is not in sync
2026-04-20 17:09:57 -03:00
canisio
286c464f5a
set SoCData as datatype again on the stream read inport (I dont know if this was the problem, but its working again)
2026-04-20 15:04:14 -03:00
canisio
91b02cdc79
organized register... stopped working
2026-04-20 11:53:26 -03:00
canisio
0b1dc081e5
commented display on PS, before testing in the board
2026-04-20 10:51:08 -03:00
canisio
d8fe924f6e
tests before trying in the board
2026-04-20 10:49:21 -03:00
canisio
b2ce956f41
Multi-frame capture integrated into full design with trigger-controlled DPW; AXI stream (uint32 [4x1]) and DMA framing aligned; fixed FSM termination condition (no overflow); validated end-to-end (PL→DMA→PS) using counter input for multiple nFrames
2026-04-17 17:03:34 -03:00
canisio
fc50e71ab5
AXI stream updated to uint32 [4x1] format; samples-per-frame aligned to nFrames×512; PS stream read configured accordingly; single-frame (nFrames=1) validated end-to-end (PL→DMA→PS) with correct unpacking and data integrity
2026-04-17 12:22:12 -03:00
canisio
ce87190fba
If sw side of AXI4-Stream to Software block is set to fixdt(128), frames appear to be arriving correctly on PS. However, reinterpretation is failing when using option "uint32"
2026-04-17 11:33:18 -03:00
canisio
cb56e78923
changed folder name for all testbench models
2026-04-17 08:31:14 -03:00
canisio
a3d46a9113
New register MF_nFrames added to PS (initialize and data genearation/capture). Not tested
2026-04-16 17:35:10 -03:00
canisio
15f20619b1
MultiFrame camputre PL part integrated (no test, no PS)
2026-04-16 17:25:28 -03:00
canisio
5e5bba3ce6
Stable 16-bit Q1.15 Rx chain before AXI width upgrade
2026-04-14 09:25:01 -03:00
canisio
ccc6b9cd73
Validate 16-bit Q1.15 Rx chain (baseline, partial validation)
...
Standardized ADC/DAC and channelizer input to fixdt(1,16,15)
Rescaled channelizer output from sFix25_En23 to 16-bit complex
Verified channelizer path and spectrum behavior in full simulation
Bypass path and datatype tuning (coefficients/output) pending validation
2026-04-13 17:47:08 -03:00
canisio
d4e53a67ee
Stable single frame (512 samples) baseline before capture redesign
2026-04-09 09:27:44 -03:00
canisio
2e570cee8b
Created folder and test bench model for new capture block. Copied from current version.
2026-04-08 15:50:59 -03:00
canisio
520a37f520
CW mode integrated to design
2026-04-08 15:00:47 -03:00
canisio
cd91e3066b
added CW mode (with LFM) to the chirp block (TB, not integrated yet)
2026-04-08 12:19:03 -03:00
canisio
5a3bc8891d
cleaned up log signals (still not working)
2026-04-07 09:26:50 -03:00
canisio
fdde9ec62b
Initiliaze funcion back to 1 (in the toggle registers). Still not working
2026-04-06 17:39:05 -03:00
canisio
84b795203a
pulse generator integrated but not working
2026-04-06 16:16:42 -03:00
canisio
ada7e324cd
Fixed register address on "update parameters"
2026-04-06 15:15:55 -03:00
canisio
7813d9744c
Modified PS part and interface towards pulse generation integration
2026-04-06 12:26:06 -03:00
canisio
05b74503dc
Fixed init callback for pulse gen testbench
2026-04-06 10:45:21 -03:00
canisio
3c6ae0cfe9
finished organization of init funcions and parameters
2026-04-04 16:05:17 -03:00
canisio
eb14676581
Oganize preload and init functions and parameters (ongoing)
2026-04-04 15:16:58 -03:00
canisio
872fbfcd6e
Minor changes
2026-04-01 11:51:59 -03:00
canisio
9794b2d540
tested on HW. Bypass ok.
2026-03-31 18:47:13 -03:00
canisio
b72a8cd616
added time scope to interface
2026-03-31 18:00:27 -03:00
canisio
f66c3ffd06
Changed interface model to reflect bypass
2026-03-31 17:51:26 -03:00
canisio
0c6938bff2
commented initialize register on proc model
2026-03-31 17:25:01 -03:00
